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1.4.6.1 Crossbar-light switch master assignments
The masters connected to the crossbar switch are assigned as follows:
Master module
Master port number
ARM core unified bus
0
DMA
2
1.4.6.2 Crossbar switch slave assignments
This device contains 3 slaves connected to the crossbar switch.
The slave assignment is as follows:
Slave module
Slave port number
Flash memory controller
0
SRAM controller
1
Peripheral bridge 0
2
1.4.7 Peripheral bridge configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
P
er
ipher
als
Transfers
AIPS-Lite
peripheral bridge
Transfers
Cr
ossbar s
witch
Figure 1-10. Peripheral bridge configuration
Table 1-18. Reference links to related information
Topic
Related module
Reference
Full description
Peripheral bridge
(AIPS-Lite)
System memory map
—
Clocking
—
Crossbar switch
Crossbar switch
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc.
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