NXP Semiconductors MIMXRT1160, Руководство по разработке аппаратного обеспечения, Страница: 8 / 24

Table 4. Clocks’ configurations (continued)
Signal name Recommended connections Description
of this forcing clock must not exceed
the VDD_SNVS_DIG level and the
frequency shall be <100 kHz under the
typical conditions.
An on-chip loose-tolerance ring
oscillator of approximately 40 kHz is
available. If RTC_XTALI is tied to GND
and RTC_XTALO is floating, the on-chip
oscillator is engaged automatically.
When a high-accuracy real-time clock is
not required, the system may use the
on-chip 40-kHz oscillator. The tolerance
is ±50 %. The ring oscillator starts faster
than the external crystal and is used
until the external crystal reaches a stable
oscillation. The ring oscillator also starts
automatically if no clock is detected at
RTC_XTALI at any time.
2. XTALI/XTALO
For the precision 24-MHz oscillator,
connect a fundamental-mode crystal
between XTALI and XTALO. An typical
80 ESR crystal rated for a maximum drive
level of 250 μW is acceptable.
Alternately, a typical 50 ESR crystal rated
for a maximum drive level of 200 μW may
be used.
For the RT1170 24-MHz OSCILLATOR,
the smaller the ESR, the better the
startup and power consumption.
To use the high-power mode, populate
the 1-Mohm resistor between XTALI
and XTALO. The SDK software requires 24 MHz on
XTALI/XTALO.
The crystal can be eliminated if an
external 24-MHz oscillator is available
in the system. In this case, please refer
to section of Bypass Configuration (24
MHz) from the reference manual. For
the bypass mode pin connection, the
external bypass clock can be put in from
EXTAL pin, at the same time, XTALO can
be used as other functions.
The logic level of this forcing clock must
not exceed the VDD_LPSR_ANA level.
If this clock is used as a reference
for the USB and Ethernet, then there
are strict frequency tolerance and jitter
requirements. The +-50 ppm accuracy
is required for the Ethernet while the
+-100 ppm accuracy is required for the
USB. See the OSC24M chapter and the
relevant interface specification chapters
for details.
3.CLK1_P/CLK1_N Internal use only These pins are used for NXP internal
testing. The CLK1_P and CLK1_N pair
should be left floating.
5 Debugging and programming
This section provides the JTAG interface summary and recommendations for using the JTAG, SWD debug, and Serial downloader
I/O.
NXP Semiconductors
Debugging and programming
Hardware Development Guide for the MIMXRT1160/1170 Processor , Rev. 2, 09/2021
User Guide 8 / 24