NXP Semiconductors MIMXRT1160 Скачать руководство пользователя страница 22

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Table 12. Recommended connections for unused analog interfaces (continued)

Module

Ball Name

Recommendations if Unused

not required). Leakage is typically 45 μA but could be a few hundred μA
at high temperature.

VDD_MIPI_1P8

For lowest leakage, 10 kΩ resistor to ground. For possible easier layout
but higher leakage, tie directly to power (inductors and capacitors are
not required). Leakage is typically 45 μA but could be a few hundred μA
at high temperature.

MIPI_DSI_CKN, MIPI_DSI_CKP,
MIPI_DSI_DN0, MIPI_DSI_DP0,
MIPI_DSI_DN1, MIPI_DSI_DP1

Not connected

MIPI_CSI_CKN, MIPI_CSI_CKP,
MIPI_CSI_DN0, MIPI_CSI_DP0,
MIPI_CSI_DN1, MIPI_CSI_DP1

Not connected

DCDC

DCDC_IN, DCDC_IN_Q,
DCDC_DIG, DCDC_ANA

Not connected

DCDC_DIG_SEANSE,
DCDC_ANA_SENSE,
DCDC_LP, DCDC_LN

Not connected

DCDC_PSWITCH,
DCDC_MODE

To ground

USB

USB1_DN, USB1_DP,
USB1_VBUS, USB2_DN,
USB2_DP, USB2_VBUS

Not connected

VDD_USB_1P8

Tie directly to power; capacitors are not required.

VDD_USB_3P3

Tie directly to power; capacitors are not required.

SYS OSC

XTALI, XTALO

Not connected

For unused digital IO, suggest to tie low or configure it to pull down.

NOTE

8 Related resources

• i.MX RT1170 Crossover Processors Data Sheet for Consumer Products (document

IMXRT1170CEC

)

• i.MX RT1170 Crossover Processors Data Sheet for Industrial Products (document

IMXRT1170IEC

)

• i.MX RT1170 Crossover Processors Data Sheet for Automotive Products (document

IMXRT1170AEC

)

9 Revision history

The following table summarizes the changes done to this document since the initial release.

NXP Semiconductors

Related resources

Hardware Development Guide for the MIMXRT1160/1170 Processor , Rev. 2, 09/2021

User Guide

22 / 24

Содержание MIMXRT1160

Страница 1: ... It provides various memory interfaces including SDRAM Raw NAND FLASH NOR FLASH SD eMMC Quad SPI Hyper RAM Flash It also provides a wide range of other interfaces for connecting external peripherals such as WLAN BluetoothR GPS displays and camera sensors Like other i MX processors i MX RT1170 also has rich audio and video features including MIPI CSI DSI LCD display graphics accelerator camera inte...

Страница 2: ...ball P11 VDD_SNVS_IN 1 Place under ball U12 VDD_SNVS_ANA 1 Place under ball U14 VDD_SNVS_DIG 1 Place under ball T14 VDD_USB_1P8 1 Place under ball H12 isolate from 1V8 source with series ferrite bead 120 ohm 100MHz VDD_USB_3P3 1 Place under ball G12 isolate from 3V3 source with series ferrite bead 120 ohm 100MHz VDDA_ADC_1P8 1 Place under ball K15 VDDA_ADC_3P3 1 Place under ball J13 VDDA_1P0 1 Pla...

Страница 3: ...2 μF1 Notes VDD_SOC_IN_x 2 3 1 Place 0402 under balls H8 J8 J9 J10 K10 VDD_LPSR_IN 1 Place under ball R12 VDD_LPSR_ANA 1 Place under ball P12 VDD_LPSR_DIG 1 Place under ball P11 VDDA_ADC_3P3 1 1 Place 1 μF under ball J13 place 0 1 μF near J13 isolate from 3V3 source with series ferrite bead 120 ohm 100MHz ADC_VREFH 1 Place under ball G16 VDDA_ADC_1P8 1 1 Place 1 μF under ball K15 place 4 7 μF near...

Страница 4: ...μF 2 2 μF and 4 7 μF are size 0402 and 22 μF is size 0805 Type X6S is used for automotive cluster and extended temperature range Table 3 Power supply and SNVS domain signals Item Recommendation Description 1 Power sequence Comply with the power up power down sequence guidelines as described in the data sheet to guarantee a reliable operation of the device Any deviation from these sequences may res...

Страница 5: ...tage limitation The common limitation for the ripple noise shall be less than 5 Vp p of the supply voltage average value The related power rails affected are VDD_XXX VDD_XXX_IN VDDA_1P0 VDD_XXX_ANA VDD_XXX_DIG 4 Supply currents Maximum supply currents comply with maximum supply currents in data sheet Concerning i MX RT1170 The DCDC_DIG_X output power capacity is 850 mA and DCDC_ANA_X output power ...

Страница 6: ...d ESR 0 1 Ω The external bulk capacitor total is about 66 μF this includes all the capacitors used on DCDC_DIG_X and VDD_SOC_IN DCDC_PSWITCH should delay 1 ms with respect to DCDC_IN to guarantee that DCDC_IN is stable before the DC DC starts up If you want to bypass the internal DC DC DCDC_PSWITCH and DCDC_MODE must be tied to the ground others signals such as DCDC_IN DCDC_LP DCDC_LN DCDC_ANA DCD...

Страница 7: ...pacitance Do not use an external biasing resistor because the bias circuit is on the chip To hit the exact oscillation frequency the board capacitors must be reduced to account for the board and chip parasitics The integrated oscillation amplifier is self biasing but relatively weak Care must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the power or the ground 100...

Страница 8: ...tartup and power consumption To use the high power mode populate the 1 Mohm resistor between XTALI and XTALO The SDK software requires 24 MHz on XTALI XTALO The crystal can be eliminated if an external 24 MHz oscillator is available in the system In this case please refer to section of Bypass Configuration 24 MHz from the reference manual For the bypass mode pin connection the external bypass cloc...

Страница 9: ... not use an external pull down on an input that has an on chip pull up External resistors can be used with all JTAG signals except for JTAG_TDO but they are not required See Table 5 for a summary of the JTAG interface 3 JTAG_MOD JTAG_MOD is called SJC_MOD in some documents Both names refer to the same signal JTAG_MOD shall be externally connected to GND for normal operation in a system The termina...

Страница 10: ...CFG 11 0 The BOOT_CFG signals are required for a proper functionality and operation and shall not be left floating during development if BOOT_CFG fuses and BT_FUSE_SEL are not configured See the System Boot chapter in your chip reference manual for the correct boot configuration Note that an incorrect setting may result in an improper boot sequence 2 BOOT_MODE 1 0 For logic 0 Tie to GND through 10...

Страница 11: ...boot sequence POR_B signal has internal 100K pull up to SNVS domain should pull up to VDD_SNVS_ANA if need to add external pull up resistor otherwise it will cause additional leakage during SNVS mode It s recommended to add the external reset IC to the circuit to guarantee POR_B is properly processed during power up down please refer to the EVK design for details Note 1 As the Low DCDC_IN detectio...

Страница 12: ...eripheral PinMux Peripheral Instance Port IO function PAD Mode Note LPUART 1 LPUART1_TX GPIO_AD_24 ALT0 Can be used for serial downloader mode Refer to Serial Downloader in Reference Manual for more information LPUART1_RX GPIO_AD_25 ALT0 LPSPI 1 LPSPI1_SCK GPIO_AD_28 ALT0 Serial NOR EEPROM connected to one of the LPSPI ports can be used as a recovery device Refer to Recovery devices in Reference M...

Страница 13: ...IO_EMC_B1_34 ALT0 SEMC_DATA13 GPIO_EMC_B1_35 ALT0 SEMC_DATA14 GPIO_EMC_B1_36 ALT0 SEMC_DATA15 GPIO_EMC_B1_37 ALT0 SEMC_ADDR09 GPIO_EMC_B1_18 ALT0 SEMC_ADDR11 GPIO_EMC_B1_19 ALT0 SEMC_ADDR12 GPIO_EMC_B1_20 ALT0 SEMC_BA1 GPIO_EMC_B1_22 ALT0 SEMC_CSX0 GPIO_EMC_B1_41 ALT0 uSDHC 1 USDHC1_CD_B GPIO_AD_32 ALT4 eMMC MMC or SD eSD connected to one of the USDHC ports is a primary boot option Refere to Expan...

Страница 14: ...l for more information The ROM will read the 512 byte FlexSPI NOR configuration parameters described in FlexSPI Serial NOR Flash Boot Operation Reference Manual using the non italicized pins Note These pins are a secondary pinout option for FlexSPI serial NOR flash boot FLEXSPI1_B_DATA 2 GPIO_SD_B2_01 ALT1 FLEXSPI1_B_DATA 1 GPIO_SD_B2_02 ALT1 FLEXSPI1_B_DATA 0 GPIO_SD_B2_03 ALT1 FLEXSPI1_B_SCLK GP...

Страница 15: ...Note ROM can configure the italicized signals based on the FlexSPI NOR configuration parameters provided FLEXSPI2_B_DATA 6 GPIO_EMC_B2_00 ALT4 FLEXSPI2_B_DATA 5 GPIO_EMC_B2_01 ALT4 FLEXSPI2_B_DATA 4 GPIO_EMC_B2_02 ALT4 FLEXSPI2_B_DATA 3 GPIO_EMC_B2_03 ALT4 FLEXSPI2_B_DATA 2 GPIO_EMC_B2_04 ALT4 FLEXSPI2_B_DATA 1 GPIO_EMC_B2_05 ALT4 FLEXSPI2_B_DATA 0 GPIO_EMC_B2_06 ALT4 FLEXSPI2_B_DQS GPIO_EMC_B2_07...

Страница 16: ...I in Reference Manual for more information The ROM will read the 512 byte FlexSPI described in FlexSPI Serial NOR Flash Boot Operation in Reference Manual using the non italicized pins Note ROM can configure the italicized signals based on the FlexSPI NOR configuration parameters provided FLEXSPI_B_DATA2 GPIO_SD_B1_01 ALT1 FLEXSPI_B_DATA1 GPIO_SD_B1_02 ALT1 FLEXSPI_B_DA TA0 GPIO_SD_B1_03 ALT1 FLEX...

Страница 17: ...NOR Flash Boot Operation in Reference Manual using the non italicized pins For 8 bit wide memories the FLEXSPI_B_DATA 3 0 pins are combined with the FLEXSPI_A_DATA 3 0 lines to get the full 8 bit port FlexSPI NOR configuration parameters provided FLEXSPI_B_DATA2 GPIO_SD_B 1_01 ALT1 FLEXSPI_B_DATA1 GPIO_SD_B1_02 ALT1 FLEXSPI_B_DATA0 GPIO_SD_B1_03 ALT1 FLEXSPI_B_SCLK GPIO_SD_B1_01 ALT1 FLEXSPI_B_DQS...

Страница 18: ...ss required impedance and required current for power traces The stackup also determines the constraints for routing and spacing Consider the following when designing the stackup and selecting the material for your board The board stackup is critical for the high speed signal quality Preplan the impedance of the critical traces The high speed signals must have reference planes on adjacent layers to...

Страница 19: ...ww nxp com Use the NXP design strategy for power and decoupling 7 3 FlexSPI FlexSPI is a flexible SPI Serial Peripheral Interface host controller which supports two SPI channels and up to 4 external devices Each channel supports Single Dual Quad Octal mode data transfer 1 2 4 8 bidirectional data lines FlexSPI is the most commonly used external memory Please refer to section FlexSPI parameters fro...

Страница 20: ...ne slots or anti etch When placing the connectors make sure that the ground plane clearouts around each pin have ground continuity between all pins Maintain the parallelism skew matched between DP and DM and match the overall differential length difference to less than 5 mils Maintain the symmetric routing for each differential pair Do not route the DP and DM traces under the oscillators or parall...

Страница 21: ...GND plane must be directly under the crystal associated components and traces The clocks or strobes that are on the same layer need at least 2 5 spacing from the adjacent traces 2 5 height from the reference plane to reduce crosstalk All synchronous modules must have the bus length matching and relative clock length control For the SD module interfaces Match the data clock and CMD trace lengths le...

Страница 22: ...CDC_ANA_SENSE DCDC_LP DCDC_LN Not connected DCDC_PSWITCH DCDC_MODE To ground USB USB1_DN USB1_DP USB1_VBUS USB2_DN USB2_DP USB2_VBUS Not connected VDD_USB_1P8 Tie directly to power capacitors are not required VDD_USB_3P3 Tie directly to power capacitors are not required SYS OSC XTALI XTALO Not connected For unused digital IO suggest to tie low or configure it to pull down NOTE 8 Related resources ...

Страница 23: ...ain signals in Table 3 Power supply and SNVS domain signals Removed the figure Power up and power down sequences Updated power sequence requirements Updated the on chip termination values and added a footnote in Table 5 JTAG interface summary Updated the description of JTAG_TDO in Table 6 JTAG recommendation Removed an item For the RT1170 SEMC module to support SDRAM SEMC_DQS pin GPIO_EMC_B1_39 sh...

Страница 24: ...ly check security updates from NXP and follow up appropriately Customer shall select products with security features that best meet rules regulations and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal regulatory and security related requirements concerning its products regardless of any inf...

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