NXP Semiconductors MC9S08LG16, Справочное руководство

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MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 337
Chapter 18
Development Support
18.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip flash and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins. Debug is done
through commands fed into the target MCU through the single-wire background debug interface. The
debug module provides a means to selectively trigger and capture bus information so an external
development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without
having external access to the address and data signals.
18.1.1 Forcing Active Background
The method for forcing active background mode depends on the specific HCS08 derivative. For the
MC9S08LG32 series, you can force active background after a power-on reset by holding the BKGD pin
low as the device exits the reset condition. You can also force active background by driving BKGD low
immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.
Other causes of reset, including an external pin reset or an internally generated error reset ignore the state
of the BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD pin, the
MCU will always reset into normal operating mode.
18.1.2 Module Configuration
The alternate BDC clock source is the ICSLCLK. To select this clock source, clear the CLKSW bit in the
BDCSCR register. For details on ICSLCLK, see
Section 11.4, “Functional Description .”