NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 16 Internal Clock Source (S08ICSV3)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 235
r
3-2
CLKST
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
Output of FLL is selected.
01 FLL Bypassed, Internal reference clock is selected.
10 FLL Bypassed, External reference clock is selected.
11 Reserved.
1
OSCINIT
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
0
FTRIM
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
1
Refer to NOTE in Section 11.1, “Introduction .”
Table 11-7. DCO frequency range
1
1
The resulting bus clock frequency should not exceed the maximum specified bus
clock frequency of the device.
DRS DMX32 Reference range FLL factor DCO range
00 0 31.25 - 39.0625 kHz 512 16 - 20 MHz
1 32.768 kHz 608 19.92 MHz
01 0 31.25 - 39.0625 kHz 1024 32 - 40 MHz
1 32.768 kHz 1216 39.85 MHz
10 0 31.25 - 39.0625 kHz 1536 48 - 60 MHz
1 32.768 kHz 1824 59.77 MHz
11 Reserved
Table 11-6. ICS Status and Control Register Field Descriptions (continued)
Field Description