NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 177
Figure 9-12. LCD Clock Tree
An external 32.768 kHz clock input is required to achieve lowest power consumption.
The value of LCDCLK is important because it is used to generate the LCD module frame frequency.
Equation 9-1 provides an expression for the LCD module frame frequency calculation.
The LCD module frame frequency is a function of the LCD module duty cycle as shown in Equation 9-1 .
Table 9-13 and Table 9-12 show LCD module frame frequency calculations that consider several possible
LCD module configurations of LCLK[2:0] and DUTY[2:0].
The LCD module frame frequency is defined as the number of times the LCD segments are energized per
second. The LCD module frame frequency must be selected to prevent the LCD display from flickering
(LCD module frame frequency is too low) or ghosting (LCD module frame frequency is too high). To
avoid these issues, an LCD module frame frequency in the range of 28 to 58 Hz is required. LCD module
frame frequencies less than 28 Hz or greater than 58 Hz are out of specification, and so are invalid.
Selecting lower values for the LCD base and frame frequency results in lower current consumption for the
LCD module.
The LCD module base clock frequency is the LCD module frame frequency multiplied by the number of
backplane phases that are being generated. The number of backplane phases is selected using the
DUTY[2:0] bits. The LCD module base clock is used by the backplane sequencer to generate the LCD
waveform data for the enabled phases (A-H).
Blink Rate
Blink Frequency
LCLK[2:0]
÷
2 x (4+LCLK[2:0]) x Y)
÷
(2
12+BRATE[2:0]
)
÷
(DUTY+1)
÷12∗
(2
LADJ[1:0]
)
LCD Charge Pump Clock
Source
LCDCLK
÷
4
LADJ[1:0]
BRATE[2:0]
LCD Base Clock
Alternate Clock
OSCOUT = 32.768 kHz
SOURCE
LCD Frame Frequency