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NXP Semiconductors
MC56F80000-EVKUM
MC56F80000-EVK Board User Manual
RXD1
TXD1
USB_+D
USB_- D
VBUS
VDD_2102
P5V_USB2
VDD
VDD
R158
0
5
V
D
-
D
+
I
D
G
US B_MICROAB_RECEP TACLE
J 26
1
2
3
4
S
2
5
S
1
S
3
S
4
R157
0
DNP
DNP
R130
4.7K
L3
330 OHM
1
2
C88
0.1 µF
R131
10K
C87
0.1 µF
U16
CP 2102N-A02-GQFN28
DNP
VREGIN
7
V
D
D
6
G
N
D
3
VBUS
8
D-
5
D+
4
RST
9
SUSPEND
12
SUSPEND
11
RI/CLK
2
DCD
1
DTR
28
DSR
27
TXD
26
RTS
24
CTS
23
NC
10
CHREN
13
CHR1
14
CHR0
15
GPIO_3/WAKEUP
16
GPIO_2/RS485
17
GPIO_1/RXT
18
GPIO_0/TXT
19
GPIO_6
20
GPIO_5
21
GPIO_4
22
RXD
25
E
P
A
D
2
9
R132
10K
C86
4.7 µF
TP 20
TP 21
C85
4.7 µF
GC11
GC12
S HIELD
Figure 19. CP2102N USB-to-UART device using SCI1 interface circuit diagram
CP2102N pin
MC56F80748 pin
Description
RXD
GPIOC11 (TXD1)
QSCI1 transmit data output on DSC
TXD
GPIOC12 (RXD1)
QSCI1 receive data input on DSC
Table 20. CP2102N pin connections
2.12 Debug
2.12.1 JTAG interface
The MC56F80748 processor has five GPIO pins multiplexed with the four JTAG signals
and one reset signal. The reset signal and JTAG signals used by the processor are:
•
RESETB input (default signal on GPIOD4 pin)
•
TMS input (default signal on GPIOD3 pin)
•
TCK input (default signal on GPIOD2 pin)
•
TDO output (default signal on GPIOD1 pin)
•
TDI input (default signal on GPIOD0 pin)
The GPIOD[4:0] signals are connected on the MC56F80000-EVK board to the 14-pin
JTAG connector (J10).
The following table describes the JTAG header pinout.
Pin number
Signal name
Description
1
GPIOD0/TDI
TAP data In
2
GND
Ground
3
GPIOD1/TDO
TAP data out
4
GND
Ground
5
GPIOD2/TCK
TAP clock
Table 21. JTAG header (J10) pinout
MC56F80000-EVKUM
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© 2022 NXP B.V. All rights reserved.
User manual
Rev. 1 — 14 December 2022
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