UM11029
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User manual
Rev. 1.0 — 16 June 2017
429 of 515
NXP Semiconductors
UM11029
Chapter 24: LPC84x Multi-Rate Timer (MRT)
24.5.2 One-shot interrupt mode
The one-shot interrupt generates one interrupt after a one-time count. With this mode, you
can generate a single interrupt at any point. This mode can be used to introduce a specific
delay in a software task.
When the timer is in the idle state, writing a non-zero value IVALUE to the INTVALn
register immediately loads the time interval value IVALUE - 1, and the timer starts to count
down. When the timer reaches 0, an interrupt is generated and the timer stops and enters
the idle state.
While the timer is running in the one-shot interrupt mode, you can perform the following
actions:
•
Update the INTVALn register with a new time interval value (>0) and set the LOAD bit
to 1. The timer immediately reloads the new time interval, and starts counting down
from the new value. No interrupt is generated when the TIME_INTVALn register is
updated.
•
Write a 0 to the INTVALn register and set the LOAD bit to 1. The timer immediately
stops counting and moves to the idle state. No interrupt is generated when the
INTVALn register is updated.
24.5.3 One-shot bus stall mode
The one-shot bus stall mode stalls the bus interface for 3 cycles of the system
clock. For the Cortex-M0+, this mode effectively stops all CPU activity until the MRT has
finished counting down to zero. At the end of the count-down, no interrupt is generated,
instead the bus resumes its transactions. The bus stall mode allows to halt an application
for a predefined amount of time and then resume, as opposed to creating a software loop
or polling a timer. Since in bus-stall mode, there are no bus transactions while the MRT is
counting down, the CPU consumes a minimum amount of power during that time.
Typically, this mode can be used when an application must be idle for a short time (in the
order of
μ
s or 10 to 50 clock cycles) - for example when compensating for a settling time
and thus no CPU activity is required.
For longer wait times, use the one-shot interrupt mode, which allows other enabled
interrupts to be serviced.
Remark:
Because the MRT resides on the APB, the total amount of wait cycles inserted in
bus stall mode, 3 cycles have to be added to IVALUE to account for the AHB-to-APB
bridge.
24.6 Register description
The reset values shown in
are POR reset values.
