UM11029
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User manual
Rev. 1.0 — 16 June 2017
237 of 515
NXP Semiconductors
UM11029
Chapter 13: LPC84x Pin interrupts/pattern match engine
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Bit0: Setting this bit will select pattern matches to generate the pin interrupts in
place of the normal pin interrupt mechanism.
For this example, pin interrupt 0 will be asserted when a match is detected on the
first product term (which, in this case, is just a high level on input 1).
Pin interrupt 2 will be asserted in response to a match on the second product term.
Pin interrupt 5 will be asserted when there is a match on the third product term.
Pin interrupt 7 will be asserted on a match on the last term.
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Bit1: Setting this bit will cause the RxEv signal to the ARM CPU to be asserted
whenever a match occurs on ANY of the product terms in the expression.
Otherwise, the RXEV line will not be used.
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Bit31:24: At any given time, bits 0, 2, 5 and/or 7 may be high if the corresponding
product terms are currently matching.
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The remaining bits will always be low.
13.7.3 Pattern match engine edge detect examples
Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the
system clock for simplicity.
Fig 18. Pattern match engine examples: sticky edge detect
IN0
SRC0 = 0, CFG0 = 0x3, PROD_ENPTS0 = 0x0 (sticky rising edge detection)
IN1
SRC1 = 1, CFG1 = 0x7, PROD_ENPTS1 = 0x1 (non-sticky edge detection)
NVIC pin interrupt 1
and GPIO_INT_BMAT output
system clock
slice 0 (IN0re)
slice 1 (IN1ev)
minterm
(IN0re)(IN1ev)
pin interrupt raised on
falling edge on input 1 any time
after IN0 has gone HIGH
