NXP Semiconductors LPC84x, Руководство пользователя

Страница: 14 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 14 of 515
NXP Semiconductors
UM11029
Chapter 3: LPC84x Boot Process
The boot ROM structure should be included as follows:
typedef struct {
const uint32_t reserved0; /*!< Reserved */
const uint32_t reserved1; /*!< Reserved */
const uint32_t reserved2; /*!< Reserved */
const PWRD_API_T *pPWRD; /*!< Power API function table base address */
const ROM_DIV_API_T *divApiBase; /*!< Divider API function table base address */
} LPC_ROM_API_T;
#define ROM_DRIVER_BASE (0x0F001FF8)
3.6 Functional description
3.6.1 Memory map after any reset
The boot ROM block is 16 KB in size. The boot block is located in the memory region
starting from address 0x0F00 0000. The bootloader is designed to run from this memory
area, but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is
described in
Section 4.3.7 “ISP interrupt and SRAM use” . The interrupt vectors residing in
the boot block of the on-chip flash memory also become active after reset, i.e., the bottom
512 bytes of the boot block are also visible in the memory region starting from the address
0x0000 0000.
Table 4. API calls
API Description Reference
Flash IAP Flash In-Application programming Table 37
Integer divider API 32-bit integer divide routines Table 471