NXP Semiconductors LPC43Sxx, Руководство пользователя

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User manual Rev. 2.1 — 10 December 2015 185 of 1441
NXP Semiconductors
UM10503
Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)
13.6.5.2 PLL1 control register
Table 138. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description
Bit Symbol Value Description Reset
value Access
0 PD PLL1 power down 1 R/W
0 PLL1 enabled
1 PLL1 powered down
1 BYPASS Input clock bypass control 1 R/W
0 Normal. CCO clock sent to post-dividers. Use
for normal operation.
1 Input clock. PLL1 input clock sent to
post-dividers (default).
2 - Reserved. Do not write one to this bit. 0 R/W
5:3 - Reserved. Do not write one to these bits. - -
6 FBSEL PLL feedback select (see Figure 40 “PLL1
block diagram” ).
0 R/W
0 CCO out. CCO output is used as feedback
divider input clock.
1 PLL out. PLL output clock (clkout) is used as
feedback divider input clock. Use for normal
operation.
7 DIRECT PLL direct CCO output 0 R/W
0 Disabled
1 Enabled
9:8 PSEL Post-divider division ratio P. The P-divider
applied by the PLL is 2xP. 01 R/W
0x0 P = 1
0x1 P = 2 (default)
0x2 P = 4
0x3 P = 8
10 - Reserved - -
11 AUTOBLOCK Block clock automatically during frequency
change 0 R/W
0 Disabled. Autoblocking disabled
1 Enabled. Autoblocking enabled
13:12 NSEL Pre-divider division ratio N 10 R/W
0x0 1
0x1 2
0x2 3 (default)
0x3 4
15:14 - Reserved - -