NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 160 of 1441
NXP Semiconductors
UM10503
Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC)
12.2.4 Power-down mode
In Power-down mode the CPU clock and peripheral clocks are shut down but logic states
are maintained. All SRAM memory except for the upper 8 kB of the local SRAM located at
0x1008 0000, all analog blocks, and the BOD control circuit are powered down.
•
Switch the clock source of all base clocks to the IRC.
•
Put the PLLs in power-down mode.
Remark: Before entering Power-down mode, program the CGU as follows:
Reprogramming the CGU avoids any undefined or unlocked PLL clocks at wake-up and
minimizes power consumption during Power-down mode.
To enter Power-down mode, follow these steps:
1. In the
PD0_SLEEP0_HW_ENA register, enable Power-down mode for the M4 core or the M0
cores.
2. In the
PD0_SLEEP0_MODE register,
write the Power-down value
0x0030 FCBA.
3. In the ARM Cortex core control register for the core or cores enabled in step 1, set the
SLEEPDEEP bit.
4. Issue a WFI or WFE instruction for the core or cores enabled in step 1.
The part can wake up from Power-down mode through a signal on any of the WAKEUP
pins or a signal from the alarm timer or RTC. Enable the wake-up signals in the event
router. See
Section 10.4 .
When the LPC43xx wakes up from Power-down mode, the 12 MHz IRC is used as the
clock source for all base clocks.
12.2.5 Deep power-down
In Deep power-down mode the entire core logic is powered down and the logic state of the
entire system including the I/O pads is lost. Only the logic in the RTC power domain
remains active.
To enter Deep power-down mode, follow these steps:
1. In the
PD0_SLEEP0_HW_ENA register, enable Power-down mode for the M4 core or the M0
cores or both.
2. In the
PD0_SLEEP0_MODE register,
write the Deep power-down value
0x0030 FF7F.
3. In the ARM Cortex core control register for the core or cores enabled in step 1, set the
SLEEPDEEP bit.
4. Issue a WFI or WFE instruction for the core or cores enabled in step 1.
When the LPC43xx wakes up from Deep power-down mode, the boot loader configures
the PLL1 as the clock source running at 96 MHz and attempts to boot in the same way as
after a reset or power-up.
The part can wake up from Deep power-down mode through a signal on any of the
WAKEUP pins or a signal from the alarm timer or RTC. See
Section 10.4 .