NXP Semiconductors LPC2880, Руководство пользователя

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UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 110 of 362
NXP Semiconductors
UM10208
Chapter 8: LPC2800 EMC
11. SDRAM initialization
Follow the following steps to initialize the EMC and one or more connected SDRAM(s)
after power-on reset:
1. Wait 100 ms after power is applied and the system clocks have stabilized.
2. Write 0x183 to the EMCDynamicControl Register. This value sends a NOP command
to the SDRAM(s), and continuous clock and clock enable.
Wait 200 ms.
3. Write 0x103 to the EMCDynamicControl Register. This changes the command to the
SDRAM(s) to PALL (precharge all).
4. Write 0x01 to the EMCDynamicRefresh Register. This makes refreshing go as fast as
possible, once every 16 AHB HCLKs.
5. Wait for eight refresh cycles (128 AHB HCLKs).
6. Write the EMCDynamicRefresh Register again, this time with the appropriate value
for the SDRAM(s). Section 8–10.5
7. Write the EMCDynamicRasCas Register with the appropriate value for the
SDRAM(s). Section 8–10.19
8. Write all of the other dynamic memory timing registers with the appropriate values for
the SDRAM(s) and clock frequencies. See sections Section 8–10.6 through
Section 8–10.17 .
9. Write the EMCDynamicConfig Register with the appropriate Address Mapping value
for the SDRAM(s). Bit 3 of this register selects between High Performance and Low
Power mode. Leave the Buffer Enable bit 0 for now. See
Table 8–96 .
10. Write 0x083 to the EMCDynamicControl Register. This changes the command to the
SDRAM(s) to MODE, which allows programming the Mode register in the SDRAM.
11. The Mode register(s) in the SDRAM(s) is (are) programmed by reading a particular
address in the SDRAM address range. Consult the SDRAM data sheet for the format
of its Mode register. Since the LPC288x uses a 16-bit-wide data bus for SDRAM, the
burst length field in the Mode register should select 8. The Burst Type field should
indicate Sequential, the Operating Mode field should select Standard operation, and
the Write Burst Mode field (if used) should also select 8. The CAS Latency field
depends on the frequency on the CLKOUT signal to the SDRAM.
Having selected a value for the Mode register, the value should be the Row address
for a read operation in the SDRAM address range. (The Bank Address bits should be
0 for programming the Mode register, so there’s no need to worry about where they’re
located in the memory address.) The location of the row address within the overall
memory address depends on the Address Mapping value used in step 9, which in turn
depends on the type of SDRAM(s). The fourth and third column from the right in
Table 8–96 show the location of the Row address within the memory address, for
BRC and RBC-type SDRAMs of various sizes. Position the value for the Mode
register in those bits as specified in the SDRAM data sheet. Leave all other address
bits 0, except add 0x3000 0000 or 0x5000 0000 to select the SDRAM address range.
Read that address to program the mode register.