UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
56 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
In general, larger vlaues of F
REF
result in a more stable PLL when the input clock is a low
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm.
Remember that when a frequency below about 1 MHz is used as the PLL clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
of this exmaple are supported, as may be confirmed in
If PLL calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit. Multiplier values one count off
from calculated values may also be good possibilities..
The value written to PLLCFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
3.2.14 PLL setup sequence
The following sequence must be followed step by step in order to have the PLL initialized
an running:
1. Disconnect the PLL with one feed sequence if PLL is already connected.
2. Disable the PLL with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without the PLL, if
desired.
4. Write to the Clock Source Selection Control register to change the clock source.
5. Write to the PLLCFG and make it effective with one feed sequence. The PLLCFG can
only be updated when the PLL is disabled.
6. Enable the PLL with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do
this before connecting the PLL.
8. Wait for the PLL to achieve lock by monitoring the PLOCK bit in the PLLSTAT register,
or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL is
slow (i.e. 32 kHz). The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
9. Connect the PLL with one feed sequence.
It's very important not to merge any steps above. For example, don't update the PLLCFG
and enable the PLL simultaneously with the same feed sequence.
3.3 Clock dividers
The output of the PLL must be divided down for use by the CPU and the USB block.
Separate dividers are provided such that the CPU frequency can be determined
independently from the USB block, which always requires 48 MHz with a 50% duty cycle
for proper operation (see