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DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
549 of 808
1.
Basic configuration
The ADC is configured using the following registers:
1. Power: In the PCONP register (
), set the PCADC bit.
Remark:
On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN
). To disable
the ADC, first clear the PDN bit, and then clear the PCADC bit.
2. Clock: In the PCLKSEL0 register (
), select PCLK_ADC. To scale the clock
for the ADC, see bits CLKDIV in
.
3. Pins: Enable ADC0 pins through PINSEL registers. Select the pin modes for the port
pins with ADC0 functions through the PINMODE registers (
).
4. Interrupts: To enable interrupts in the ADC, see
. Interrupts are enabled
in the NVIC using the appropriate Interrupt Set Enable register. Disable the ADC
interrupt in the NVIC using the appropriate Interrupt Set Enable register.
5. DMA: See
. For GPDMA system connections, see
2.
Features
•
12-bit successive approximation analog to digital converter.
•
Input multiplexing among 8 pins.
•
Power-down mode.
•
Measurement range 0 V to V
REFP
(typically 3 V; not to exceed V
DDA
voltage level).
•
12-bit conversion rate of 200 kHz.
•
Burst conversion mode for single or multiple inputs.
•
Optional conversion on transition on input pin or Timer Match signal.
3.
Description
Basic clocking for the A/D converters is provided by the APB clock. A programmable
divider is included in each converter to scale this clock to the clock (maximum 13 MHz)
needed by the successive approximation process. A fully accurate conversion requires 65
of these clocks.
4.
Pin description
gives a brief summary of each of ADC related pins.
UM10360
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
Rev. 00.06 — 5 June 2009
User manual