UM10503
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User manual
Rev. 1.3 — 6 July 2012
727 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
26.7.3.4 Receive path functions
The MAC captures the timestamp of all frames received on the MII. The MAC does not
process the received frames to identify the PTP frames in the default mode, that is, when
the Advanced Timestamp feature is not selected.
The MAC gives the timestamp and the corresponding status on the MAC Receive
Interface (MRI) along with the EOF data. The MAC transaction layer (MTL) provides the
timestamp on the data bus after the EOF data has been transferred. The MTL sends a
separate signal to validate the timestamp and to indicate the availability of the timestamp.
Once the timestamp is transferred, the Status Valid signal is asserted as soon as status
data is present on the data bus.
The DMA returns the timestamp to the software in the corresponding receive descriptor.
The 64-bit timestamp information is written back to the RDES6 and RDES7 fields. The
RDES2 holds the 32 least significant bits of the timestamp, except as mentioned in
. The timestamp is written only to that receive descriptor for which the
Last Descriptor status field has been set to 1 (the EOF marker). When the timestamp is
not available (for example, because of an RxFIFO overflow), an all-ones pattern is written
to the descriptors (RDES6 and RDES7), indicating that timestamp is not correct. If the
software uses a control register bit to disable time stamping, the DMA does not alter
RDES6 or RDES7.
26.7.3.5 Timestamp error margin
According to the IEEE 1588 specifications, a timestamp must be captured at the SFD of
the transmitted and received frames at the MII interface. Because the reference timing
source (the PTP clock) is different from the MII clocks, a small error margin is introduced,
because of the transfer of information across asynchronous clock domains.
In the transmit path, the captured and reported timestamp has a maximum error margin of
2 PTP clocks. It means that the captured timestamp has the reference timing source value
that is given within 2 clocks after the SFD has been transmitted on the MII.
Similarly, in the receive path, the error margin is 3 MII clocks, plus up to 2 PTP clocks. You
can ignore the error margin because of the II clocks by assuming that this constant delay
is present in the system (or link) before the SFD data reaches the GMAC.s MII interface.
26.7.3.6 Frequency range of the reference timing clock
The timestamp information is transferred across asynchronous clock domains, that is,
from MAC clock domain to application clock domain. Therefore, a minimum delay is
required between two consecutive timestamp captures. This delay is 4 clock cycles of II
and 3 clock cycles of PTP clocks. If the delay between two timestamp captures is less
than this delay, the MAC does not take a timestamp snapshot for the second frame.
The maximum PTP clock frequency is limited by the maximum resolution of the reference
time (1 ns resulting in 1 GHz) and the timing constraints achievable for logic operating on
the PTP clock. In addition, the resolution, or granularity, of the reference time source
determines the accuracy of the synchronization. Therefore, a higher PTP clock frequency
gives better system performance.
