UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
360 of 1269
NXP Semiconductors
UM10503
Chapter 18: LPC43xx Serial GPIO (SGPIO)
18.6.8 Position registers (POS0 to 15)
Each position register contains the position counter for one slice: POS0 to POS15 contain
the counter for slice A (register 0) to slice P (register 15).
This register controls when the shadow register REG_SS content is exchanged with main
register REG.
To exchange content every k x 32 bit, POS_PRESET should be 0x20 x k -1. This setting
should be used when k slices are concatenated (CONCAT_ENABLE is set).
Remark:
Before a slice is started (using CTRL_ENABLE), POS should be set to the
POS_PRESET value.
18.6.9 Slice A mask register (MASK_A)
18.6.10 Slice H mask register (MASK_H)
18.6.11 Slice I mask register (MASK_I)
Table 222. Position registers (POS0 to 15, addresses 0x4010 11C0 to 0x4010 11FC) bit
description
Bit
Symbol
Description
Reset
value
Access
7:0
POS
Each time COUNT reaches 0x0 POS counts
down.
0
R/W
15:8
POS_RESET
Reload value for POS after POS reaches 0x0.
0
R/W
31:16
-
Reserved.
-
-
Table 223. Slice A mask register (MASK_A, address 0x4010 1200) bit description
Bit
Symbol
Description
Reset
value
Access
31:0
MASK_A
Mask for pattern match function of slice A
0 = No effect.
1 = Mask this bit.
0
R/W
Table 224. Slice H mask register (MASK_H, address 0x4010 1204) bit description
Bit
Symbol
Description
Reset
value
Access
31:0
MASK_H
Mask for pattern match function of slice H
0 = No effect.
1 = Mask this bit.
0
R/W
Table 225. Slice I mask register (MASK_I, address 0x4010 1208) bit description
Bit
Symbol
Description
Reset
value
Access
31:0
MASK_I
Mask for pattern match function of slice I
0 = No effect.
1 = Mask this bit.
0
R/W