UM10503
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User manual
Rev. 1.3 — 6 July 2012
14 of 1269
NXP Semiconductors
UM10503
Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process
The basic IPC features are:
•
The ARM Cortex-M4 initializes the ARM Cortex-M0 system.
•
The ARM Cortex-M4 communicates with the ARM Cortex-M0 system via a command
queue.
•
The message queues are located in the ARM Cortex-M4 address space because the
ARM Cortex-M4 can be blocked from access to the ARM Cortex-M0 hardware
subsystem.
2.5.1 IPC queues
The ARM Cortex-M4 has an output command queue and an input message queue. A
queue is defined by four registers:
1. queue start address
2. queue end address
3. write pointer
4. read pointer
The ARM Cortex-M4 initializes these four registers. These registers reside in the same
shared SRAM as the queues to ensure that data and registers changes are synchronous.
Their location is static and known up front by the ARM Cortex-M0.
Messages are passed through queues using cyclic buffers. A queue is filled with
commands or messages from start to end address. When a buffer pointer points beyond
the end address it wraps around to the start address. When the read pointer is equal to
the write pointer, the queue can be either empty or completely full. To avoid this ambiguity
the queue shall never be filled completely. The minimum queue size is thus 3 words (the
longest command/m1 word). An equal write and read pointer will indicate an
empty queue.
The command queue is filled by the ARM Cortex-M4 and emptied by the ARM Cortex-M0;
the write pointer is advanced by the ARM Cortex-M4 every time it adds a new command
to the queue. The read pointer is advanced by the ARM Cortex-M0 every time it removes
a command from the queue.
The message queue is filled by the ARM Cortex-M0 and emptied by the ARM Cortex-M4;
the write pointer is advanced by the ARM Cortex-M0 every time it adds a new message to
the queue. The read pointer is advanced by the ARM Cortex-M4 every time it removes a
message from the queue.
When a new command or message has been added to the queue and the write pointer
had been updated, an interrupt is raised to the other processor. The commands are
acknowledged by a return message (accept or fail).
The ARM Cortex-M4 and ARM Cortex-M0 only have one IPC write and one IPC read task.
If multiple instances exist then a local arbiter shall ensure that all write and read
operations are atomic; after data has been written (read) the write (read) pointer is
updated before another write (read) operation can start.
