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28.1.2.3 Debug Mode
Entry to debug mode has no effect on the EWM.
• If the EWM is enabled prior to entry of debug mode, it remains enabled.
• If the EWM is disabled prior to entry of debug mode, it remains disabled.
28.1.3 Block Diagram
This figure shows the EWM block diagram.
Clock Divider
Logic
LPO_CLK
Low Power
Clock
Clock Gating
Cell
AND
Enable
EWM_CTRL[EWMEN]
EWM_CLKPRESCALER[CLK_DIV]
8-bit Counter
OR
Counter Value
Reset to
Counter
EWM Refresh
And
/EWM_out Output
Control
Mechanism
EWM_CMPH[COMPAREH]
EWM_CMPL[COMPAREL]
EWM Refreshed
EWM_out
Counter
overflow
EWM_in
EWM Service Register
CPU
Reset
Figure 28-1. EWM Block Diagram
Chapter 28 External Watchdog Monitor (EWM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors
595
Содержание Kinetis KE1xZ256
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