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47.2.3 Block Diagram
The following diagram gives a high-level overview of the configuration of FlexIO timers
and shifters.
31
0
SHIFTBUF0
SHIFTER0
31
0
SHIFTBUFi
SHIFTERi
FXIO_Dn
out/outen
FXIO_Dn
in
TIMER0
TIMERi
External Triggers
Input
Selection
Output
Selection
Timer
Selection
Figure 47-1. FlexIO block diagram
47.2.4 Modes of operation
The FlexIO module supports the chip modes described in the following table.
Table 47-2. Chip modes supported by the FlexIO module
Chip mode
FlexIO Operation
Run
Normal operation
Stop/Wait
Can continue operating provided the Doze Enable bit (CTRL[DOZEN]) is set and
the FlexIO is using an external or internal clock source which remains operating
during stop/wait modes.
Debug
Can continue operating provided the Debug Enable bit (CTRL[DBGE]) is set.
Chapter 47 Flexible I/O (FlexIO)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors
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