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NXP Semiconductors
JN-RM-2080
K32W module development reference manual
JN-RM-2080
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Reference manual
Rev. 1.0
— 27 Mar 2020
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Ground pours or fingers can act as antennas that unintentionally radiate. To avoid this,
eliminate any finger that is not connected to the ground reference with a via; put a via in
any trace that doesn’t go anywhere.
4.7 Layers interconnections
Avoid vias in the RF traces. Typically for a 1.6mm thickness PCB material, a single via
can add 1.2nH of inductance and 0.5pF of capacitance, depending upon the via
dimensions and PCB dielectric material.
Provide multiple vias for high current and/or low impedance traces.
Connect carefully all the ground areas of any layer to the reference GND plane
4.8 DCDC components
Be sure that the smallest values capacitors C12 and C10 are placed close to the VBAT
pin.
The impedance of the GND connection between C10/C12 and C19 must be as low as
possible: connect them directly on the component layer (see the red path below)
The R2 footprint on DCDC reference design can be removed if there is constraint on the
layout space as long as the DCDC is used as depicted in the current K32W061/041
datasheet.
C
1
0
C
1
2
C
19
Fig 9.
GND path between C10/C12 and C19
