NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 1087 / 1379

SCG_SPLLDIV field descriptions (continued)
Field Description
SPLLDIV1 System PLL Clock Divide 1
Clock divider 1 for System PLL. Used to generate the clock source for modules that need an
asynchronous clock source.
000 Clock disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
42.2.21 System PLL Configuration Register (SCG_SPLLCFG)
The SPLLCFG register cannot be changed when the System PLL is enabled. When the
System PLL is enabled, writes to this register are ignored, and there is no transfer error.
The below information applies to VCO_CLK.
The SPLL_CLK = (VCO_CLK)/2
The VCO_CLK = SPLL_SOURCE/( 1) X (MULT + 16)
SPLL_SOURCE is the clock source selected from the SOURCE bitfield of this register.
Address: 4007_B000h base + 608h offset = 4007_B608h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
MULT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PREDIV
0
SOURCE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 42 System Clock Generator (SCG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1087