NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
27
4.9 FLASH Registers and Control Bits
The FLASH module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in
FLASH memory which are copied into three corresponding high-page control registers at reset. There is also an 8-byte
comparison key in FLASH memory. Refer to
Table 8 and Table 9 for the absolute address assignments for all FLASH registers.
This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file
normally is used to translate these names into the appropriate absolute addresses.
4.9.1 FLASH Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 can be read at any time but can be written only once. Before any
erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory
system within acceptable limits.
$1820 7 6 5 4 3 2 1 0
R
DIVLD
PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
W
Reset:
0 0 0 0 0 0 0 0
= Reserved
Figure 12. FLASH Clock Divider Register (FCDIV)
Table 10. FCDIV Register Field Descriptions
Field Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been written since
reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written.
0
FCDIV has not been written since reset; erase and program operations disabled for FLASH
1 FCDIV has been written since reset; erase and program operations enabled for FLASH
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8
5:0
DIV[5:0]
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock divided by 8 if
PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal FLASH clock must fall
within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase timing pulses are one cycle of this internal
FLASH clock which corresponds to a range of 5

s to 6.7

s. The automated programming logic uses an integer number of
these pulses to complete an erase or program operation.
• if PRDIV8 = 0 — f
FCLK
= f
Bus

([DIV5:DIV0] + 1)
• if PRDIV8 = 1 — f
FCLK
= f
Bus

(8

([DIV5:DIV0] + 1))
Table 11 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
Table 11. FLASH Clock Divider Settings
f
Bus
PRDIV8
(Binary)
DIV5:DIV0
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5

s Min, 6.7

s Max)
20 MHz 1 12 192.3 kHz 5.2

s
10 MHz 0 49 200 kHz 5

s
8 MHz 0 39 200 kHz 5

s
4 MHz 0 19 200 kHz 5

s
2 MHz 0 9 200 kHz 5

s
1 MHz 0 4 200 kHz 5

s
200 kHz 0 0 200 kHz 5

s
150 kHz 0 0 150 kHz 6.7

s