NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
21
None of the RAM locations are used directly by the firmware provided by Freescale. The firmware routines utilize RAM only
through stack operations; and the user needs to be aware of stack depth required by each routine as described in the
CodeWarrior project files supplied by Freescale.
4.7 FLASH
The FLASH memory is intended primarily for program storage. The operating program can be loaded into the FLASH memory
after final assembly of the application product using the single-wire BACKGROUND DEBUG interface. Because no special
voltages are needed for FLASH erase and programming operations, in-application programming is also possible through other
software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to
the
HCS08 Family Reference Manual, Volume I, Freescale document order number HCS08RMV1/D.
4.7.1 Features
Features of the FLASH memory include:
• User Program FLASH Size — 8192 bytes (16 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for FLASH and RAM
• Auto power-down for low-frequency read accesses
4.7.2 Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the
internal clock for the FLASH module to a frequency (f
FCLK
) between 150 kHz and 200 kHz. This register can be written only once,
so normally this write is performed during reset initialization. FCDIV cannot be written if the access error flag, FACCERR in
FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting
clock (1/f
FCLK
) is used by the command processor to time program and erase pulses. An integer number of these timing pulses
are used by the command processor to complete a program or erase command.
Table 9 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (f
FCLK
). The time
for one cycle of FCLK is t
FCLK
= 1/f
FCLK
. The times are shown as a number of cycles of FCLK and as an absolute time for the
case where t
FCLK
= 5

s. Program and erase times shown include overhead for the command state machine and enabling and
disabling of program and erase voltages.
4.7.3 Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared
before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into
the FLASH interface. This write is a required first step in any command sequence. For erase and blank check
commands, the value of the data is not important. For page erase commands, the address may be any address in the
512-byte page of FLASH to be erased. For mass erase and blank check commands, the address can be any address
in the FLASH memory. Whole pages of 512 bytes are the smallest block of FLASH that may be erased.
Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits to a
byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass
erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH.
Table 9. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45

s
Byte program (burst) 4 20

s
(1)
1. Excluding start/end overhead
Page erase 4000 20 ms
Mass erase 20,000 100 ms