NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
20 Freescale Semiconductor, Inc.
4.4 High Address Registers
High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in
the direct page for more frequently used registers and variables. The registers control system level features as given in
Table 8 .
4.5 MCU Parameter Registers
The 64 bytes of parameter registers are located at addresses $0050 through $008F. These registers are powered up at all times
and may be used to store temporary or history data during the times that the MCU is in any of the STOP modes. The parameter
register at $008F is used by the firmware for interrupt flags.
4.6 MCU RAM
The FXTH870xD includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct
addressing mode, and any single bit in this area can be accessed with the bit-manipulation instructions (BCLR, BSET, BRCLR,
and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power WAIT, STOP3 or STOP4 modes. At power-on or after wakeup from STOP1,
the contents of RAM are not initialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below
the minimum value for RAM retention (V
RAM ).
When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code
executing from non-secure memory. See
Section 4.8 for a detailed description of the security feature.
Table 8. MCU High Address Register Summary
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$1800 SRS POR PIN COP ILOP ILAD PWU LVD 0
$1801 SBDFR 0 0 0 0 0 0 0 BDFR
$1802 SIMOPT1 COPE COPCLKS STOPE RFEN TRE TRH BKGDPE 1
$1803 SIMOPT2 0 COPT[2:0] LFOSEL TCLKDIV BUSCLKS[1:0]
$1804 Reserved
$1805 Reserved
$1806 SDIDH REV[3:0] ID[11:8]
$1807 SDIDL ID[7:0]
$1808 SRTISC RTIF RTIACK RTICLKS RTIE 0 RTIS{2:0]
$1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 BGBE
$180A SPMSC2 0 0 0 PDF 0 PPDACK PDC 0
$180B Reserved
$180C SPMSC3 LVWF LVWACK LVDV LVWV 0 0 0 0
$180D SIMSES KBF IRQF TRF PWUF LFF RFF
$180E SOTRM SOTRM[7:0]
$180F SIMTST TRH[2:0] TRO
$1810-1F Reserved
$1820 FCDIV DIVLD PRDIV8 DIV[5:0]
$1821 FOPT KEYEN FNORED 0 0 0 0 SEC0[1:0}
$1822 Reserved
$1823 FCNFG 0 0 KEYACC 0 0 0 0 0
$1824 FPROT FPS[7:1] FPDIS
$1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
$1826 FCMD FERASE FCMD[6:0]
$1827-3F Reserved
Note: Reserved bits shown as 0 must always be written to 0.
Reserved bits shown as 1 must always be written to 1.
Shaded bits are recommended to only be controlled by firmware or factory test.