NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
129
13.18 PLL Control Registers B- PLLCR[3:2], RPAGE = 0
The PLLCR[3:2] registers contain 16 control bits for the RFM as described in Figure 108 . These bits are only accessible when
the RPAGE bit is cleared.
1:0
CODE
[1:0]
Data Encoding and Source - The CODE[1:0] control bits select the type of data encoding and source of data for the RF output.
The CODE[1:0] control bits are cleared by the RFMRST signal.
00
Manchester encoded data from the RFM data buffer.
01 Bi-Phase encoded data from the RFM data buffer.
10 NRZ direct data from the RFM data buffer (can be mixed NRZ and Manchester at 2X the data rate).
11 MCU direct mode with RF output driven by the state of the DATA bit.
$003A Bit 7 6 5 4 3 2 1 Bit 0
R
BFREQ[12:5]
W
RFMRST:
0 0 0 0 0 0 0 0
$003B
R
BFREQ[4:0] CF MOD CKREF
W
RFMRST:
0 0 0 0 0 0 0 0
Figure 108. PLL Control Registers B (PLLCR[3:2], RPAGE = 0)
Table 83. PLLCR[3:2] Field Descriptions
Field Description
PLLCR2
7:0
BFREQ
12:5
PLLCR3
7:3
BFREQ
4:0
PLL Divider Ratio B - The BFREQ[12:0] control bits select the PLL divider ratio for a data one in either the OOK or FSK modes
of modulation as described by the following equation:
where:
f
CARRIER
= RF Carrier frequency in MHz
f
XTAL
= External crystal frequency in MHz
CF = State of the CF carrier select bit
BFREQ = Decimal value of the BFREQ[12:0] binary weighted bits
The BFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of BFREQ[12:0] = 3.17 kHz.
2
CF
Carrier Frequency - The CF control bit selects the optimal VCO setup and correct divider for the 500 kHz reference clock to the
MCU on D
X
based on the external crystals required for the desired carrier frequency. The CF control bit is cleared by the
RFMRST signal.
0
Configured for 315 MHz, 12.1154 PLL divider using a 26.000 MHz external crystal.
1 Configured for 434 MHz, 16.6923 PLL divider using a 26.000 MHz external crystal.
1
MOD
RF Modulation Method - The MOD control bit selects the method of modulating the RF. The MOD control bit is cleared by the
RFMRST signal.
0
Configured for OOK.
1 Configured for FSK.
0
CKREF
Generated Clock Reference - Generates the DX signal to the TPM1 module for determining the other
clock frequencies:
0
D
X
signal not generated.
1 D
X
500 kHz signal connected to the TPM1 module.
Table 82. PLLCR[1:0] Field Descriptions (continued)
Field Description
f
DATA1
f
XTAL
12 4 CF

+
 
BFREQ
8192
--------------------
+
 
 

=