NXP Semiconductors FXTH870 D Series, Руководство пользователя

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FXTH870xD
Sensors
128 Freescale Semiconductor, Inc.
13.17 PLL Control Registers A- PLLCR[1:0], RPAGE = 0
The PLLCR[1:0] registers contain 16 control bits for the RFM as described in Figure 107 . These bits are only accessible when
the RPAGE bit is cleared.
3
RFIEN
RF Interrupt Enable — The RFIEN bit enables the RFIF, the RFEF and the RFVF bits to generate an interrupt to the MCU. The
RFMRST signal clears this bit.
0 RF interrupts disabled.
1 RF interrupts enabled.
2
RFLVDEN
RF LVD Enable — When the RFLVDEN bit is set, the RF LVD circuit will be enabled, and the RF LVD events are routed to the
RF LVD Trigger Flag. This bit is cleared by the RFMRST signal.
0
RF LVD disabled.
1 RF LVD enabled.
1
RCTS
RF Clear To Send Status — When the RCTS bit is set the RF XCO, VCO and PLL have started and locked and the RFM is ready
to send data. This bit is cleared by the RFMRST signal.
0
RFM not ready to send.
1 RFM ready to send.
0
RFMRST
RFM Reset — Writing a one to the RFMRST bit will completely reset the RFM and its registers. This bit is not affected by a reset
of the MCU. This bit will always read as a zero.
0
No effect.
1 Reset RFM.
$0038 Bit 7 6 5 4 3 2 1 Bit 0
R
AFREQ[12:5]
W
RFMRST:
0 0 0 0 0 0 0 0
$0039
R
AFREQ[4:0] POL CODE
W
RFMRST:
0 0 0 0 0 0 0 0
Figure 107. PLL Control Registers A (PLLCR[1:0], RPAGE = 0)
Table 82. PLLCR[1:0] Field Descriptions
Field Description
PLLCR0
7:0
AFREQ
12:5
PLLCR1
7:3
AFREQ
4:0
PLL Divider Ratio A - The AFREQ[12:0] control bits select the PLL divider ratio for a data zero in the FSK mode of modulation
as described by the following equation:
where:
f
DATA0
= RF Carrier frequency for a data zero in MHz
f
XTAL
= External crystal frequency in MHz, 26 MHz
CF = State of the CF carrier select bit
AFREQ = Decimal value of the AFREQ[12:0] binary weighted bits
The AFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of AFREQ[12:0] = 3.17 kHz.
2
POL
Data Polarity - The POL control bit selects the polarity of the data encoding selected by the CODE[1:0] bits. The POL control bit
is cleared by the RFMRST signal.
0
NRZ and MCU direct DATA bit data non-inverted and Manchester encoding polarity
as in
Figure 95 and Bi-Phase encoding polarity as in Figure 97 .
1 NRZ and MCU direct DATA bit data inverted and Manchester encoding polarity
as in
Figure 94 and Bi-Phase encoding polarity as in Figure 96 .
Table 81. RFCR7 Field Descriptions (continued)
Field Description
f
DATA0
f
XTAL
12 4 CF

+
 
AFREQ
8192
---------------------
+
 
 

=