NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

Страница: 304 / 372

MCU Timer/PWM (TPM Module)
MC1321x Reference Manual, Rev. 1.6
17-12 Freescale Semiconductor
17.6.3 Timer x Counter Modulo Registers (TPM1MODH:TPM1MODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from $0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPM1MODH or TPM1MODL inhibits the TOF bit and overflow interrupts until the other byte is
written. Reset sets the TPM counter modulo registers to $0000, which results in a free-running timer
counter (modulo disabled).
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
17.6.4 Timer x Channel n Status and Control Register (TPM1CnSC)
TPM1CnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
7 6 5 4 3 2 1 0
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0
Figure 17-7. Timer x Counter Modulo Register High (TPM1MODH)
7 6 5 4 3 2 1 0
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Figure 17-8. Timer x Counter Modulo Register Low (TPM1MODL)
7 6 5 4 3 2 1 0
R
CHnF CHnIE MSnB MSnA ELSnB ELSnA
0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 17-9. Timer x Channel n Status and Control Register (TPM1CnSC)