NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

Страница: 266 / 372

MCU Internal Clock Generator (ICG)
MC1321x Reference Manual, Rev. 1.6
14-22 Freescale Semiconductor
14.5.4 Status Register 2 (S2)
3
LOCK
FLL Lock Status — The LOCK bit indicates whether the FLL has acquired lock. The LOCK bit is cleared in Off,
Self-clocked, and FLL bypassed modes.
0
FLL is currently unlocked.
1 FLL is currently locked.
2
LOCS
Loss Of Clock Status — The LOCS bit is an indication of ICG loss-of-clock status. If LOCS is set, it remains set
until cleared by clearing the ICGIF flag or an MCU reset.
0
has not lost clock since LOCS was last cleared.
1 has lost clock since LOCS was last cleared, LOCRE determines action taken.
1
ERCS
External Reference Clock Status — The ERCS bit is an indication of whether or not the external reference
clock (ICGERCLK) meets the minimum frequency requirement.
0
External reference clock is not stable, frequency requirement is not met.
1 External reference clock is stable, frequency requirement is met.
0
IF
Interrupt Flag — The ICGIF read/write flag is set when an interrupt request is pending. It is cleared by a reset
or by reading the ICG status register when ICGIF is set and then writing a 1 to ICGIF. If another ICG interrupt
occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain set after the clear
sequence was completed for the earlier interrupt. Writing a 0 to ICGIF has no effect.
0
No interrupt request is pending.
1 An interrupt request is pending.
Offset
7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 DCOS
Write
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 14-13. Status Register 2 (S2)
Table 14-9. S2 Field Descriptions
Field Description
0
DCOS
DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error
has not changed by more than n
unlock
for two consecutive samples and the DCO clock is not static. This bit is
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used
in Self-clocked Mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the
off state.
0 DCO clock is unstable.
1 DCO clock is stable.
Table 14-8. S1 Field Descriptions (continued)
Field Description