NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

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MCU Internal Clock Generator (ICG)
MC1321x Reference Manual, Rev. 1.6
14-8 Freescale Semiconductor
14.3.5 FLL Engaged, External Clock (FEE) Mode
The FLL Engaged External (FEE) Mode is entered when any of the following conditions occur:
• CLKS = 11 and ERCS and DCOS are both high.
• The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
In FEE Mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE Mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source.
The maximum external clock frequency is limited to 10 MHz in FEE Mode to prevent over-clocking the
DCO. The minimum multiplier for the FLL, from
Table 14-7 , is 4. Because 4 X 10 MHz is 40 MHz, which
is the operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
14.3.5.1 FLL Engaged External Unlocked
FEE unlocked is entered when FEE is entered and the count error (
Δ
n) output from the subtractor is greater
than the maximum n
unlock
or less than the minimum n
unlock
, as required by the lock detector to detect the
unlock condition.
The will remain in this state while the count error (
Δ
n) is greater than the maximum n
lock
or less than the
minimum n
lock
, as required by the lock detector to detect the lock condition.
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by f
ICGDCLK
/ (2
×
R). This
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. As soon as the FLL has locked, if an unexpected loss of
lock causes it to re-enter the unlocked state while the remains in FEE Mode, the output clock signal
ICGOUT frequency is given by f
ICGDCLK
/ R.
14.3.5.2 FLL Engaged External Locked
FEE locked is entered from FEE unlocked when the count error (
Δ
n) is less than n
lock
(max) and greater
than n
lock
(min) for a given number of samples, as required by the lock detector to detect the lock
condition. The output clock signal ICGOUT frequency is given by f
ICGDCLK
/R. In FLL engaged external
locked, the filter value is only updated once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
14.3.6 FLL Lock and Loss-of-Lock Detection
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see
Table 14-2 for explanation of a comparison cycle) and passes this number
to the subtractor. The subtractor compares this value to the value in MFD and produces a count error,
Δ
n.
To achieve locked status,
Δ
n must be between n
lock
(min) and n
lock
(max). As soon as the FLL has locked,
Δ
n must stay between n
unlock
(min) and n
unlock
(max) to remain locked. If
Δ
n goes outside this range
unexpectedly, the LOLS status bit is set and remains set until acknowledged or until the MCU is reset.