Modem SPI Register Descriptions
MC1321x Reference Manual, Rev. 1.6
5-34
Freescale Semiconductor
5.36
Timestamp_B - Register 2F
The Timestamp_B Register 2F stores the least significant 16 bits of the value in the Event Timer counter
(et[23:0]) when the beginning of the most recent receive packet occurred. The value is latched immediately
following reception of the FLI field and at the beginning of the payload data.
5.37
BER_Enable - Register 30
The BER_Enable Register 30 contains the bit error rate test enable bit which allows the transceiver to be
put into continuous Receive or Transmit Mode. This feature is useful sequences in RF test configurations
(reference application note AN2976). The default condition is with the Continuous Mode disabled.
Register 2F
0x2F
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
timestamp[15:0]
TYPE
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 5-37. Register 2F Description
Name
Description
Operation
Bits 15-0
timestamp[15:0]
— 16 least significant bits of the latched 24-bit timestamp value
for the beginning of the receive packet.
Register 30
0x30
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
be
r_en
TYPE
r/w
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0x0004
Table 5-38. Register 30 Description
Name
Description
Operation
Bits 14-0
Reserved
Bit 15
ber_en
— The bit error rate test enable bit allows the
transceiver to be put into continuous Receive or Transmit
Mode. Continuous TX Mode is useful for current
measurements or for looking at TX spectrum. Continuous
RX Mode is useful for looking at current.
1 = When a TX operation or RX operation is enabled,
the transceiver stays in that operation until aborted.
0 = Continuous operation disabled; normal operation.
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