NXP Semiconductors
LPCXpresso55S36UM
LPCXpresso55S36 Development Board User Manual
2.15.3.3 Workaround
See
to determine correct J9 and J10 pins.
2.15.3.4 Fix plan
Silkscreen labels will be corrected for J9 and J10 pins in next board revision.
2.15.4 Erratum 48: DMIC PDM clock signals indicate incorrect clock
2.15.4.1 Description
In the LPC5536 MCU, the DMIC PDM clock (at the MCU pin PIO_7) uses DMIC PDM
channel 1. However, in the LPCXpresso55S36 board schematics, the DMIC PDM clock
signals are named with CLK0, instead of CLK1. For example, two DMIC PDM clock
signals are named as P0_7-PDM_CLK0_ISP1 and P0_7-PDM_CLK0_OnBoard.
2.15.4.2 Impact
DMIC PDM clock signal names are confusing.
2.15.4.3 Workaround
CLK0 in DMIC PDM clock signals in the board schematics should be read as CLK1. For
example, P0_7-PDM_CLK0_ISP1 and P0_7-PDM_CLK0_OnBoard should be read as
P0_7-PDM_CLK1_ISP1 and P0_7-PDM_CLK1_OnBoard, respectively.
2.15.4.4 Fix plan
The signal names will be corrected in the next revision of the board schematics.
2.15.5 Erratum 51: To use PDM DATA0, PDM CLK1 must be enabled
2.15.5.1 Description
On the LPCXpresso55S36 board, PDM DATA0 at the target MCU pin PIO0_27 is paired
with the PDM clock CLK1 (instead of CLK0) at the target MCU pin PIO0_7 and the PDM
data and clock signals are connected to the DMIC interface. To use PDM DATA0 at
PIO0_27, PDM CLK1 at PIO0_7 must be enabled.
2.15.5.2 Impact
The DMIC interface of the board cannot be used.
2.15.5.3 Workaround
Enable PDM CLK1 at PIO0_7 by setting the EN_CH1 bit (bit 1) of DMIC register
CHANEN to 1. Additionally, enable DMIC internal clock by configuring the PDMDIV bits of
DMIC register DIVHFCLK1.
2.15.5.4 Fix plan
No fix planned.
LPCXpresso55S36UM
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User manual
Rev. 2 — 5 September 2022
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