M0A21/M0A23 Series
May 06, 2022
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Rev 1.02
M0
A21
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A
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SE
RIES
TEC
H
NICAL
RE
FEREN
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ANUAL
Figure 6.16-8 Propagation Time Segment
In this example, both nodes A and B are transmitters, performing an arbitration for the CAN bus. Node
A has sent its Start of Frame bit less than one bit time earlier than node B, therefore node B has
synchronized itself to the received edge from recessive to dominant. Since node B has received this
edge delay (A_to_B) after it has been transmitted, B’s bit timing segments are shifted with respect to A.
Node B sends an identifier with higher priority and so it will win the arbitration at a specific identifier bit
when it transmits a dominant bit while node A transmits a recessive bit. The dominant bit transmitted by
node B will arrive at node A after the delay (B_to_A).
Due to oscillator tolerances, the actual position of node A’s Sample Point can be anywhere inside the
nominal range of node A’s Phase Buffer Segments, so the bit transmitted by node B must arrive at node
A before the start of Phase_Seg1. This condition defines the length of Prop_Seg.
If the edge from recessive to dominant transmitted by node B arrives at node A after the start of
Phase_Seg1, it can happen that node A samples a recessive bit instead of a dominant bit, resulting in
a bit error and the destruction of the current frame by an error flag.
The error occurs only when two nodes arbitrate for the CAN bus that have oscillators of opposite ends
of the tolerance range and that are separated by a long bus line. This is an example of a minor error in
the bit timing configuration (Prop_Seg is too short) that causes sporadic bus errors.
Some CAN implementations provide an optional 3 Sample Mode but the C_CAN does not. In this mode,
the CAN bus input signal passes a digital low-pass filter, using three samples and a majority logic to
determine the valid bit value. This results in an additional input delay of 1 tq, requiring a longer
Prop_Seg.
Phase Buffer Segments and Synchronization
The Phase Buffer Segments (Phase_Seg1 and Phase_Seg2) and the Synchronization Jump Width
(SJW) are used to compensate for the oscillator tolerance. The Phase Buffer Segments may be
lengthened or shortened by synchronization.
Synchronizations occur on edges from recessive to dominant, their purpose is to control the distance
between edges and Sample Points.
Edges are detected by sampling the actual bus level in each time quantum and comparing it with the
bus level at the previous Sample Point. A synchronization may be done only if a recessive bit was
sampled at the previous Sample PHardoint and if the bus level at the actual time quantum is dominant.
An edge is synchronous if it occurs inside of Sync_Seg, otherwise the distance between edge and the
end of Sync_Seg is the edge phase error, measured in time quanta. If the edge occurs before Sync_Seg,
the phase error is negative, else it is positive.
Two types of synchronization exist, Hard Synchronization and Re-synchronization.
A Hard Synchronization is done once at the start of a frame and inside a frame only when Re-
synchronizations occur.
Hard Synchronization
After a hard synchronization, the bit time is restarted with the end of Sync_Seg, regardless of the edge
phase error. Thus hard synchronization forces the edge, which has caused the hard synchronization to
lie within the synchronization segment of the restarted bit time.
Bit Re-synchronization
Re-synchronization leads to a shortening or lengthening of the bit time such that the position of the
sample point is shifted with regard to the edge.
When the phase error of the edge which causes Re-synchronization is positive, Phase_Seg1 is
lengthened. If the magnitude of the phase error is less than SJW, Phase_Seg1 is lengthened by the
magnitude of the phase error, else it is lengthened by SJW.
