ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
434
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
16
to
1
MUX
2h
3h
0h
1h
6h
7h
4h
5h
Fh
PWM_CH1 down-count compared point
PWM_CH0 zero point
PWM_CH0 period point
PWM_CH0 up-count compared point
PWM_CH0 down-count compared point
PWM_CH1 zero point
PWM_CH1 period point
PWM_CH1 up-count compared point
PWM Trigger 0/
PWM Trigger 1
PWM_CH0 up-count free compared point
PWM_CH0 down-count free compared point
PWM_CH2 up-count free compared point
PWM_CH2 down-count free compared point
PWM_CH4 up-count free compared point
PWM_CH4 down-count free compared point
9h
Ah
8h
Dh
Eh
Bh
Ch
TRGSEL0 (PWM_EADCTS0[3:0])/
TRGSEL1 (PWM_EADCTS0[11:8]
TRGEN0 (PWM_EADCTS0[7])/
TRGEN1 (PWM_EADCTS0[15])
PWM_CH1 period or zero point
PWM_CH0 period or zero point
EADC
Figure 6.8-38 PWM0_CH0 and PWM0_CH1 Pair Trigger EADC Block Diagram
PWM_CMPDATn
PWM_PERIODn
zero point trigger
PWM_CNTn
4
7
3
2
0
1
2
3
4
3
1
2
0
1
2
3
4
3
1
2
0
5
6
7
6
4
5
1
2
3
4
period point trigger
CMPU point trigger
CMPD point trigger
FTCMPU point trigger
PWM_FTCMPDATn
6
FTCMPD point trigger
Figure 6.8-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform
6.8.5.27 Capture Operation
The channels of the capture input and the PWM output share the same pin and counter. The counter
can operating in up or down counter type. The capture function will always latch the PWM counter
to the RCAPDATn (PWM_RCAPDATn[15:0]) bits or the FCAPDATn (PWM_FCAPDATn[15:0]) bits,
Содержание ISD94100 Series
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