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ISD2360 Design Guide

Release Date: Nov 20, 2014

- 50 -

Revision v1.14

9.

Register Operations

Table 9-1 Register Operations

Register Function

Name

Bit

Description

De

c

Hex

7 6 5 4 3 2 1 0

-

-

Clock

Register

Reserved

CLK_INP_SEL

Select system clock source. Use SET_CLK_REG and RD_CLK_REG to
access this register.

00 = Internal Oscillator with internal Resistor

01 = Reserved

10 = Reserved

11 = Reserved

Default

0

0 1 1 0 1

0

0 0x00 reset value. Read/Write.

-

-

Device

Status

Register

PD

Device Powered Up/Down Indicator.

1 = Device is powered down

0 = Device is powered up.

DBUF_RDY

When the device is powered up, DBUF_RDY bit reflects the state of the
RDY/BSYB pin.

INT

This bit is set by hardware each time a playback operation completes.

Must be cleared by software by a SPI READ_INT operation.

If GPIO3/INTB pin is configured as INTB function pin, when INT bit is set, an
active low interrupt is generated on INTB pin; and a SPI RED_INT operation
can set INTB pin high

.

-

Reserved

CH2_BSY

Set by hardware when Channel 2 is playing. Cleared by hardware when
Channel 2 is idle.

CH1_BSY

Set by hardware when Channel 1 is playing. Cleared by hardware when
Channel 1 is idle.

CH0_BSY

Set by hardware when Channel 0 is playing. Cleared by hardware when
Channel 0 is idle.

DIG_BSY

Set by hardware when the memory controller is busy processing memory
access. Cleared by hardware when the memory controller is idle.

Default

0

1 0 0 0 0

0

0

0x40 reset value. Read only.

Note: POI VM may change the device Status register value after reset.

-

-

Interrupt

Status

Register

-

Reserved

MPT_ERR

Set when digital access violates the memory protection scheme.

Must be cleared by software READ_INT operation.

WR_FIN

Set when digital write operation successfully completes.

Must be cleared by software READ_INT operation.

CMD_ERR

Set when the device receives an invalid command.

Must be cleared by software READ_INT operation.

OVF_ERR

Set when there is an invalid digital read/write operation when RDY/BSYB pin
is low.

Must be cleared by software READ_INT operation.

CH2_CFIN

Set when a playback completes in Channel 2.

Must be cleared by software READ_INT operation.

CH1_CFIN

Set when a playback completes in Channel 1.

Must be cleared by software READ_INT operation.

CH0_CFIN

Set when a playback completes in Channel 0.

Must be cleared by software READ_INT operation.

Default

0

0 0 0 0 0

0

0

0x00 reset value. Read only.

Note: POI VM may change the device Interrupt Status register value after
reset.

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Содержание ISD2360

Страница 1: ...ISD2360 Design Guide Publication Release Date Nov 20 2014 Revision V1 14 ISD ChipCorder ISD2360 Design Guide...

Страница 2: ...nformation please contact Nuvoton Technology Corporation at www nuvoton com Important Notice Nuvoton products are not designed intended authorized or warranted for use as components in systems or equi...

Страница 3: ...EAD WRITE 14 5 8 FAST DE BOUNCE FOR GPIO TRIGGER 15 5 9 THERMAL SHUTDOWN 15 6 OPERATIONAL DESCRIPTION 16 6 1 OVERVIEW 16 6 2 AUDIO STORAGE 16 6 3 SAMPLE RATES 16 6 4 AUDIO COMPRESSION AND DE COMPRESSI...

Страница 4: ...ay Operations 42 8 4 1 9 STOP_LP Stop Loop Play Operations 42 8 4 1 10 SPI_PCM_READ SPI Read De Compressed PCM Data from Memory 42 8 4 1 11 SPI_SND_DEC SPI Send Compressed Data for Decoding 43 8 4 2 D...

Страница 5: ...360 Design Guide Release Date Nov 20 2014 v Revision v1 14 11 2 2 Speaker Outputs 59 11 2 3 DC Parameters 60 11 2 4 SPI Timing 60 12 PACKAGE DIMENSIONS 62 13 ORDERING INFORMATION 64 14 REVISION HISTOR...

Страница 6: ...Figure 7 1 ISD2360 Memory Organization 23 Figure 7 2 Sample_Project_1 Configuration 29 Figure 7 3 Sample_Project_2 Configuration 31 Figure 7 4 Sample_Project_3 Configuration 33 Figure 8 1 SPI Data Tra...

Страница 7: ...ter Result Data Storage 13 Table 5 4 C Code Example Fletcher 32 Checksum Calculation 13 Table 5 5 Indirect Reference Registers R0 R7 14 Table 5 6 GPIO Pin and Indirect Reference Register Association 1...

Страница 8: ...wer consumption fast programming time and integrated program verification Features Performance Enhancements o 3 channel mixing playback o GPIO parallel processing supports dynamic change on GPIO outpu...

Страница 9: ...to direct drive an 8 speaker or buzzer o Delivers 1W at 5V supply o Delivers 400mW at 3V supply I Os o SPI interface MISO MOSI SCLK SSB for commands and digital audio data o 6 General Purpose I O GPI...

Страница 10: ...heat dissipation and mechanical stability NC NC GPIO0 MOSI VSSD NC NC NC NC NC NC GPIO4 RDY BSYB GPIO3 INTB NC NC NC NC NC VCC_PWM SPK VSS_PWM VSS_PWM SPK VCC_PWM NC NC SSB GPI1 SCLK GPIO2 MISO NC GPI...

Страница 11: ...the ISD2360 from the host Can be configured as a General Purpose I O pin 4 VSSD Digital Ground 5 NC This pin should remain Not Connected 6 NC This pin should remain Not Connected 7 NC This pin should...

Страница 12: ...onnected 24 NC This pin should remain Not Connected 25 NC This pin should remain Not Connected 26 VCCD I Digital Power 27 GPIO5 I O General Purpose I O pin 28 NC This pin should remain Not Connected 2...

Страница 13: ...6 VCC_PWM I Digital Power for the Pulse Wave Modulator PWM Driver 7 SPK O PWM driver positive output The SPK output and the SPK pin provide a differential output to drive an 8 speaker or buzzer Durin...

Страница 14: ...Interpreter Ch2 PWM Control SP SP Internal Flash Memory Power Conditioning VCCD VSSD VCCDPWM VSSDPWM GPI1 SCLK GPIO2 MISO GPIO3 INTB GPIO0 MOSI GPIO5 SSB GPIO4 RDY BSYB SPI Interface GPIO Interface F...

Страница 15: ...Bit 3 Bit 2 Bit 1 Bit 0 PD DBUF_RDY INT CH2_BSY CH1_BSY CH0_BSY DIG_BSY The individual bits of the Device Status Register refer to the following conditions PD If this bit is set the device is powered...

Страница 16: ...r Description Interrupt Status Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TALARM_INT MPT_ERR WR_FIN CMD_ERR OVF_ERR CH2_FIN CH1_FIN CH0_FIN The individual bits of the Interrupt Status Regist...

Страница 17: ...external components to operate This oscillator provides an internal clock source that operates the ISD2360 at a maximum audio sample rate Fsmax of 32 kHz The ISD2360 user should always use the clock f...

Страница 18: ...l standby current the GPIO triggering configuration in those 3V registers is still in effect therefore the ISD2360 can continue detecting a GPIO trigger during power down 5 3 3 GPIO Pin Structure Once...

Страница 19: ...e indicated by AF1 and AF0 then when the toggling happens the ISD2360 device will execute a wake up event 5 4 Signal Path Configuration The signal path involves filtering sample rate conversion volume...

Страница 20: ...cess Mode Value At Reset Nominal Value 0x10 0x13 R 0x0000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x10 CHK_SUM1 7 0 0x11 CHK_SUM1 15 8 0x12 CHK_SUM2 7 0 0x13 CHK_SUM2 15 8 Note that the hardware Fletc...

Страница 21: ...4 GPIO5 GPIO6 GPIO7 Associated Indirect Reference Register R0 R1 R2 R3 R4 R5 R6 R7 5 7 GPIO4 Configuration for Digital Read Write The ISD2360 implements an internal FIFO with 4 byte depth which govern...

Страница 22: ...output of nearly 1 Watt when operating at 5 V With the increase of the delivered output power the heat generated also increases To prevent the accumulating heat from burning out the device a thermal...

Страница 23: ...ile into the device Flash memory from the beginning of the Flash memory The GUI software ISD VPE2360 enables users to create the application image file Provided by Nuvoton Technology Corp the ISD VPE2...

Страница 24: ...device hardware interprets the Voice Prompt header and de compress the VP data accordingly Unless overridden ISD2360 hardware always plays the VP according to the sample rate specified in the VP heade...

Страница 25: ...igger occurs depending on if the trigger occurs in PD state the ISD2360 device will or will not execute the Wakeup Voice Macro before executing the triggering pin associated Voice Macro as shown in Fi...

Страница 26: ...triggering condition o Write Output Enable Control Register 0x1A to configure the GPIO pin as an input pin o Write Output Enable Control Register 0x1B and Pull Select Control Register 0x1D Configure...

Страница 27: ...on the user must check the device status before sending the SPI commands Unlike the SPI operation in GPIO Trigger operation the ISD2360 always executes the associated VM in the assigned channel regard...

Страница 28: ...l device The 3 channel mixer allows the user to mix audio data on any or all of the three channels By first filtering and up sampling the data from the individual channel s to an intermediate frequenc...

Страница 29: ...it can be any valid VM command anywhere within the device image MASK_GOTO is a conditional jump Refer to the Mask Jump Control register 0x08 definition the jump condition includes JBSY and JGPIOn 0 n...

Страница 30: ...data as shown in Figure 7 1 Memory Header Voice Prompts Voice Macros User Data Note that an ISD2360 application image always has a memory header and Voice Prompt data but may not have Voice Macros and...

Страница 31: ...used all 0xFF Note Byte order for PMP and VP VM addresses conforms to the Little Endian convention The Memory Header contains at least 17 bytes located at the beginning of the memory space Byte 0 dete...

Страница 32: ...ection means that digital write or erase commands such as DIG_WRITE and MEM_ERASE will not function in this memory area Note that WP protection does not block the chip erase protection Read Protect Wr...

Страница 33: ...behind this script is Write 0x44 into register Reg0x02 to enable decoder and PWM path Write 0x00 into register Reg0x03 to maximize the volume Play VP with index 0x0006 Power down the device after the...

Страница 34: ...AY_VP Rn Indirect Play VP whose index in currently in register Rn 0 n 0x07 PLAY_VP_LP i cnt Loop Play cnt times the VP with index i 0 n 0xFFFF 0 cnt 0xFFFF PLAY_VP_LP Rn cnt Indirect Loop Play cnt tim...

Страница 35: ...e use of Voice Macros to setup GPIO triggers multiple channel mixing and the multiple channel counter with mask branch to achieve GPIO PWM control The user should study the simplest project first beca...

Страница 36: ...associated with GPIO2 assign channel 0 to VM associated with GPIO3 CFG R0 0x03 write 0x03 into reg0x20 associate VM0x03 with GPIO0 CFG R1 0x04 write 0x04 into reg0x22 associate VM0x04 with GPIO1 CFG...

Страница 37: ...ll power down Note that in this VM it does not configure output path because the Wakeup VM has already done so 7 3 3 2 Sample_2 Channel Mixing with Volume Control Goal Create a GPIO trigger to play pr...

Страница 38: ...0x15 assign all channels to VM associated with GPIO4 assign channel 0 to VM associated with GPIO5 CFG GPIO_VOL_UD_SEL 0x03 write 0x03 into reg0x16 GPIO4 Trigger to volume up GPIO5 trigger to volume do...

Страница 39: ...tes VM 0x03 PD power down device to save power Because of the preemptive nature of the GPIO trigger VM 0x09 stops the play in its channel which is channel 0 Then it reassigns the GPIO0 associated VM b...

Страница 40: ...0 5 CFG REG_GPIO_AF1 0x0F write 0x0F into reg0x1E CFG REG_GPIO_AF0 0x00 write 0x00 into reg0x1F combined with reg0x1E to confiure GPIO0 3 as falling edge triggering pins GPIO4 and 5 as output pins CFG...

Страница 41: ...e user to reserve user data sectors for storage of application data other than audio When working on a VPE project an interface is available within the Reserved Memory panel for the user to specify th...

Страница 42: ...D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Z X Figure 8 1 SPI Data Transaction Waveform A transaction begins with a command byte C7 C0 with the most significant bit MSB C7 first During the byte transm...

Страница 43: ...ow when sending data to the ISD2360 or 2 invalid data from ISD2360 Refer to Figure 8 3 for the timing diagram in which RDY BSYB is ignored The following conditions must be met to avoid RDY BSYB pollin...

Страница 44: ...A STOP current playback operation STOP_LP 0x2E Stop Loop Play Voice Prompt SPI_PCM_READ 0xAC D0 7 0 D0 15 8 D1 7 0 D1 15 8 Dn 7 0 Dn 15 8 Receive 16 bit PCM audio data low byte high byte from ISD2360...

Страница 45: ...8 2 or a CMD_ERR interrupt will be generated and the command will be ignored It is a good practice to check the device status prior to sending commands to ensure the success of the SPI command Table 8...

Страница 46: ...4 1 1 PLAY_VP Play Voice Prompt PLAY_VP Byte Sequence Host Controller 0xA6 Index 15 8 Index 7 0 ISD2360 Status Byte Status Byte Status Byte Description Play Voice Prompt Index Interrupt Generation CM...

Страница 47: ...ed CMD_FIN when playback is finished This command initiates the play of a pre recorded voice prompt Before execution of the command a valid signal path must be set up and the device must have space in...

Страница 48: ...n 7 0 ISD2360 Status Byte Status Byte Description Play Voice Macro with index stored in Rn Interrupt Generation CMD_ERR if not accepted CMD_FIN when playback is finished This command initiates the exe...

Страница 49: ...n ERASE_MEM operation If there is no active command STOP will have no effect The STOP command applies to the channel set in SPI_CMD_CH When SPI_CMD_CH 3 and a STOP command is issued the STOP command a...

Страница 50: ...d is terminated If RDY BSYB is ignored then an OVF_ERR interrupt will be generated 8 4 1 11 SPI_SND_DEC SPI Send Compressed Data for Decoding SPI_SND_DEC Byte Sequence Host Controller 0xC0 D0 7 0 D1 7...

Страница 51: ...Byte Sequence Host Controller 0x40 0xXX ISD2360 Status Byte Interrupt Status Byte Description Query device status This command queries the ISD2360 device status For details see Section 4 Device Status...

Страница 52: ...DR_ERR if memory is protected or if RDY BSYB is violated OVF_ERR if the read is past the end of the array This command initiates a read of Flash memory from address A 23 0 Following the three address...

Страница 53: ...emory the CMD_BSY bit will be active Digital and Audio commands cannot occur concurrently To prevent the possibility of data corruption the user should disable any Voice Macro triggers and check the s...

Страница 54: ...eted When CHIP_ERASE is in progress the Status bit 0 CMD_BSY goes high The user may poll the status to determine if the erasing is complete 8 4 3 5 CHECKSUM Calculate Hardware Checksum CHECKSUM Byte S...

Страница 55: ...up procedure is as follows Send PWR_UP command Poll Status until bit 6 DBUF_RDY goes high which means ready If there is Power Up Voice Macro implemented poll the device status until CHx_BSY goes low w...

Страница 56: ...Host Controller 0xBA REG 7 0 X X ISD2360 STATUS0 D0 Dn Description Reads configuration register CFG REG and outputs to SPI as D0 Data bytes 1 n can be read sequentially from CFG REG 1 to CFG REG n Thi...

Страница 57: ...when Channel 1 is idle CH0_BSY Set by hardware when Channel 0 is playing Cleared by hardware when Channel 0 is idle DIG_BSY Set by hardware when the memory controller is busy processing memory access...

Страница 58: ...p control at the end of a playback 0 default value Device will ramp down at the end of playback 1 device does not ramp down at the end of a playback NSRSIL Overturn the automatic silence insertion bet...

Страница 59: ...triggering temperature i e the Talarm threshold x for don t care bit 0000 105 C 0001 115 C 001x 125 C 01xx 135 C 1xxx 145 C Default 0 0 0 1 0 0 0 0 0x10 reset value Read Write 6 06 Reserved 7 07 8 08...

Страница 60: ...0 Checksum Register CHK_SUM1_LB Holds checksum value chk_sum1 7 0 after checksum calculation Write a 1 then 0 to register 0x04 bit 4 resets all Checksum registers 0x10 0x13 to 0 Default 0 0 0 0 0 0 0...

Страница 61: ...r to up down 010 GPIO2 trigger to up down 011 GPIO3 trigger to up down 100 GPIO4 trigger to up down 101 GPIO5 trigger to up down 110 111 Reserved Default 0 0 0 0 0 0 0 0 0x00 reset value Read Write 23...

Страница 62: ...ved GPIO_PS 5 0 pull low on GPIO5 1 pull high on GPIO5 GPIO_PS 4 0 pull low on GPIO4 1 pull high on GPIO4 GPIO_PS 3 0 pull low on GPIO3 1 pull high on GPIO3 GPIO_PS 2 0 pull low on GPIO2 1 pull high o...

Страница 63: ...0 0 0 0x00 reset value Read Write 41 29 R4_H R4_H Indirect Reference Register R4 high byte value Default 0 0 0 0 0 0 0 0 0x00 reset value Read Write 42 2A R5_L R5_L Indirect Reference Register R5 low...

Страница 64: ...General Purpose Input Output GPIO pins 10 1 SPI Application under MCU Control A standard four wire Serial Peripheral Interface SPI is used for communication between the ISD2360 and the host The inter...

Страница 65: ...General Purpose Input Output GPIO pins Voice Prompt and Voice Macro commands facilitate fast programming GPIO2 MISO GPI1 SCLK SSB GPIO0 MOSI GPIO3 INTB GPIO4 RDY BSYB 29 30 31 3 21 22 VSSD VCCD VCCD...

Страница 66: ...o any pins VSS 0 3 V to VDD 0 3 V Notes 1 VDD VCCA VCCD 2 VSS VSSA VSSD 11 2 AC Paramaters 11 2 1 Internal Oscillator Parameter Symbol Min Typ Max Units Conditions Sample Rate with Internal Oscillator...

Страница 67: ...D VD D V IOH 1mA Pull up Resistance RPU 50 k Pull down Resistance RPD 10 k INTB Output Low Voltage VOH1 0 4 V Playback Current IDD_Playback 3 mA No Load 2 Standby Current ISB 1 10 A VDD 3 6V Input Lea...

Страница 68: ...LK Falling Edge Setup Time 30 ns TSSBH Last SCLK Rising Edge to SSB Rising Edge Hold Time 30 ns 50 s TSSBHI SSB High Time between SSB Lows 20 ns TMOS MOSI to SCLK Rising Edge Setup Time 15 ns TMOH SCL...

Страница 69: ...014 62 Revision v1 14 12 Package Dimensions The ISD2360 is available in a QFN 32 Lead package as shown in Figure 12 1 and an SOP 16 Lead package as shown in Figure 12 2 1 8 8 9 16 1 16 17 17 9 24 24 3...

Страница 70: ...ISD2360 Design Guide Release Date Nov 20 2014 63 Revision v1 14 Figure 12 2 SOP 16 Lead Package...

Страница 71: ...e Date Nov 20 2014 64 Revision v1 14 13 Ordering Information I23XX Y Y I Duration 60 64 Seconds Based on 8 kHz 4 bit ADPCM Lead Free Y Green Package Type Y 32 Lead QFN S 16 Lead SOP 300 mil Temperatur...

Страница 72: ...2012 First release 1 11 August 23 2012 SOP 16 Lead device Replaced pin diagram added pin descriptions Commercial Parts Operating Conditions removed Linguistic and format changes 1 12 March 05 2013 SPI...

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