Registers Format
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3.2 A/D Data Registers
ACL-8111 provides 8 single-end A/D input channels. The 12 bit A/D data is
put in two 8-bit registers. The low byte date (8 LSBs) is at address BASE+4
and the high byte data (4 MSBs) is at address BASE+5. The DRDY bit is
used to indicate the status of A/D conversion. DRDY goes to low-level
means A/D conversion is completed.
Address : BASE + 4 and BASE + 5
Attribute: read only
Data Format:
Bit
7
6
5
4
3
2
1
0
BASE+4
AD7
AD6
AD5 AD4 AD3 AD2 AD1 AD0
BASE+5 0 0 0
DRDY
AD11 AD10 AD9 AD8
AD11. AD0: Analog to digital data. AD11 is the Most Significant Bit (MSB).
AD0 is the Least Significant Bit (LSB).
DRDY: Data Ready Signal.
1: A/D data is not ready
0: A/D conversion is completed.
It will be set to 1 after reading out the low byte data
