DA70131-1/3E
III-10
2) Uses the
_____
WRQ
output (CPU has a wait function)
Note: The memory area (078h to 1FFh when the I/F mode = 4) is shared with the internal serial reception
circuit. In order to prevent a conflict between reading by a CPU and the internal timing, the center
device transfers data from the memory area (internal RAM) to an indirect reading buffer, and then
reads the data from this buffer.
In order to secure the necessary data transfer time (2 clock cycles at 40 MHz), the center device
outputs
_____
WRQ
= L in response to
____
RD
= L, when reading the memory area. Please note the output
delay time for reading data. (For details about the output delay time, see section 7-4, "AC
characteristics" in the G9001A manual.)
1-2-2. Access by commands
The center device has 9 address terminals used to access 512 bytes of memory. The access timing for each of
these addresses is shown below. However, for certain CPUs, this amount of memory is not directly available.
In this case, just use three address terminals to access 8 bytes in the center device. When addressing in this
fashion, commands are used to access addresses beyond the basic 8 bytes.
The access timing used to access the memory area in the center device with commands is different from the
method used for direct memory address.
However, CPU's with a wait function don't need to be aware of these timing requirements, since they use the
_____
WRQ
terminal on the center device.
For CPUs that don't have a wait function, monitor the
____
IFB output or use software to observe the timing described
below (this is essential).
Data
Data
Next address
Address
Address
___
CS
___
RD
____
WRQ
DATA
The CPU automatically waits for the
required period of time.
Содержание Motionnet G9001A
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