DA70131-1/3E
I-42
7-4-6. I/F mode 1 (IF1=L, IF0=L) (16-bit 68000 etc.)
- Read cycle
- Write cycle
Note 1: When CKSL = LOW or CKSL = HIGH, the
_______
DTACK
signal LOW level will be held for MIN = 4 x T
CLK,
MAX = 28T
CLK
+ 15.
Note 2: When CKSL = LOW or CKSL = HIGH, the
_______
DTACK
signal LOW level will be held for MIN = 4 x T
CLK,
MAX = 20T
CLK
+ 15.
Note 3: When CKSL = LOW or CKSL = HIGH, the data float delay time will be 4T
CLK
.
Item
Symbol
Condition
Min.
Max.
Unit
Address setup time for
____
LS
↓
T
AS
17
ns
Address hold time for
____
LS
↑
T
SA
0
ns
____
CS
setup time for
____
LS
↓
T
CSS
10
ns
____
CS
hold time for
____
LS
↑
T
SCS
0
ns
R/
___
W
setup time for
____
LS
↓
T
RWS
2
ns
R/
___
W
hold time for
____
LS
↑
T
SRW
14
ns
_______
DTACK
=ON delay time for
____
LS
↓
T
SLAKR
C
L
= 40pF Note 1
2T
CLK
14T
CLK
+15
ns
T
SLAKW
C
L
= 40pF Note 2
2T
CLK
10T
CLK
+15
ns
_______
DTACK
=ON delay time for
____
LS
↑
T
SHAKR
C
L
= 40pF
7
ns
T
SHAKW
C
L
= 40pF
7
ns
Data float delay time for ACK
↓
T
DAKLR
C
L
= 40pF Note 3
2T
CLK
ns
Data float delay time for
____
LS
↑
T
SHD
C
L
= 40pF
14
ns
Data setup time for
____
LS
↑
T
DSL
22
ns
Data hold time for ACK
↓
T
AKDH
0
ns
A(8:1)
___
LS(A0)
R/
___
W (
___
WR)
D(15:0)
_______
DTACK(
_____
WRQ)
A(8:1)
D(15:0)
T
AS
T
CSS
T
RWS
T
SLAKR
T
SA
T
SCS
T
SRW
T
SHAKR
T
DAKLR
T
SHD
T
AS
T
CSS
T
RWS
T
SLAKW
T
DSL
T
AKDH
T
SHAKW
T
SRW
T
SCS
T
SA
___
CS
___
CS
___
LS(A0)
_______
DTACK(
_____
WRQ)
R/
___
W (
___
WR)
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