DA70131-1/3E
I-38
7-4. AC characteristics
7-4-1. Reference clock
1) When setting CKSL = L
Item
Symbol
Min.
Standard
Max.
Unit
Frequency
f
CLK
-
40
40
MHz
Cycle
T
CLK
-
25
25
ns
HIGH duration
T
CLKH
10
12.5
15
ns
LOW duration
T
CLKL
10
12.5
15
ns
Note: In order to secure good communication quality, use a clock offering the nearest figures to the
standards above.
For details, see the "CLK" section of the "terminal function" in this manual.
2) When setting CKSL = H
Item
Symbol
Min.
Standard
Max.
Unit
Frequency
f
CLK
-
-
80
MHz
Cycle
T
CLK
-
-
12.5
ns
HIGH duration
T
CLKH
-
-
-
ns
LOW duration
T
CLKL
-
-
-
ns
7-4-2. Reset timing
Item
Symbol
Min.
Standard
Max.
Unit
Reset length
T
WRSTI
10
-
-
Clock cycles
Delay time
T
DRST
-
10
-
Clock cycles
Note 1: The reset signal must last at least 10 cycles of the reference clock.
While resetting, make sure that the clock signal is continuously available to the device.
If the clock is stopped while resetting, the device cannot be reset normally.
Note 2: After the internal RST goes LOW, the center device automatically resets the internal memory area to all
zeros (address: 078h to 1ffh). After the reset is complete, the center device is once again ready.
During the reset, the status RBSY (bit 13) remains 1. Therefore, make sure that this bit has returned to 0 before
accessing the center device at the end of a reset.
The following are the minimum times needed to reset the internal memory area.
CKSL = L --- 270 T
CLK
(6.75
μsec at 40 MHz)
CKSL = H --- 540 T
CLK
(6.75
μsec at 80 MHz)
____
RST
T
DRST
T
WRSTI
Internal
RST
T
DRST
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