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DA70131-1/3E
I-10
4-4. Functions of terminals
4-4-1. CLK
This is an input terminal of the reference clock. By setting of the CKSL terminal, either of the following clock rate
signals can be connected.
CKSL = L: 40 MHz
CKSL = H: 80 MHz
By selecting either of these clock rates, the serial communication transfer rate does not change. This clock rate
selection affects communication precision.
For a small-scale serial communication and transfer rate below 10 Mbps, use of the center device with 40 MHz
does not give any restriction.
With 20 Mbps transfer speed; however, longer communication lines or a large number of connected local devices
may deteriorate communication precision due to collapse of signals on the circuit. This deterioration of
communication quality can be corrected inside the LSI, if the deterioration level is not much. In order to improve
correction precision; however, evenness of the clock duty is required. In other words, if the duty is ideal (50:50), the
capacity to correct collapse of the signals in the communication lines can be improved. On the contrary, if the duty
is not ideal, the center device cannot cope with collapses of the communication line.
As a result, if the duty is close to ideal, the center device can be used with 40 MHz. When connecting more than
one oscillator, the duty will not be ideal. In this case, select 80 MHz. The center device divides the frequency inside
and creates 40 MHz frequency.
If you do not want to use 80 MHz frequency, you may prepare a separate 40 MHz oscillator for this LSI.
4-4-2.
____
RST
This is an input terminal for a reset signal.
By inputting an L level signal, the center device is reset. As the center device synchronizes with a clock, arrange a
circuit so that it does not disconnect the clock while resetting. Reset signal length longer than 10 clock cycles is
required.
4-4-3. CKSL
Use to select clock rate.
L: Connect 40 MHz clock frequency to the CLK terminal.
H: Connect 80 MHz clock frequency to the CLK terminal.
Select this when the duty of the 40 MHz clock collapses too much.
4-4-4. IF0, IF1
Specify CPU-I/F mode
Set status
I/F mode
CPU signal to connect to terminals
Example of CPU
IF1
IF0
____
RD
terminal
____
WR
terminal
A0
terminal
_____
WRQ
terminal
L
L
I/F mode 1
(VDD)
R/W
_____
LDS
________
DTACK
68000
L
H
I/F mode 2
____
RD
_____
HWR
(VDD)
_______
WAIT
H8
H
L
I/F mode 3
____
RD
____
WR
(GND)
READY
8086
H
H
I/F mode 4
____
RD
____
WR
A0
_______
WAIT
Z80
This LSI has the following four interface modes.
The above four CPUs are typical ones among CPUs currently available on the market. Even if a CPU you are
examining is other than the above CPUs, most of the CPUs can be connected using either of the interfaces above.
For details, see the hardware specification sheets of the CPU you are planning to use, and check with which mode
you can connect.
Note: The classification of the CPU interface modes above is applicable only for the center device. The CPU
emulation device G9004A also has unique CPU interface modes. Mode classification of this is different than
the above.
Содержание Motionnet G9001A
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