UPP_WD2 voltage/clock frequency adjusting
No external clock is available for UPP_WD2 before VCXO starts. As reset is released, the VCXO is running and MCU
uses the 26 MHz clock while DSP is in reset. There are three identical DPLL's, for MCU, for DSP and for accessory
interfaces, which can be controlled independently. The clock for MCU can be up to 130 MHz and 156 MHz is
maximum clock frequency for the DSP. These clock signals are used either directly (SDRAM IF) or divided down
for the interfaces (e.g. flash IF).
Power distribution, control and reset
All power (except backup battery power) is drawn from the BL-4C Li-Ion battery located in the B cover. Current
flows through ZOCUS current sense resister which is used for current measurement by ZOCUS and thus for
remaining operating time estimation.
1FSA board contains one power ASIC, UEME and discrete regulators needed for generating the different
operating voltages. The discrete regulators consist of an SMPS to power UPP_WD2 voltage core. In addition,
there is a SMPS in 1FSA generating the operating voltage for display module backlighting. In 1FSA, the keyboard
backlight is powered with a charge pump regulator.
There is also a “soft watchdog” in UPP_WD2. It is used to reset the chip in case software gets stuck for any reason.
Power-up sequence (reset mode)
RESET mode can be entered in four ways: by inserting the battery or charger, by RTC alarm or by pressing the
power key. The VCXO is powered by UEME. After a 220 ms delay, regulators are configured and UEME enters
PWR_ON mode and system reset PURX is released.
During the system start-up, in RESET state, the regulators are enabled, and each regulator charges the capacitor
(s) at the output with the maximum current (short circuit current) it can deliver. This results in battery voltage
dropping during start-up. When a battery with a voltage level just above the hardware cutoff limit is inserted,
the system may not start due to excessive voltage dipping. Dropping below 2.8 V for longer than 5 us forces
the system to PWR_OFF state.
Powering off
Controlled powering off is done when the user requests it by pressing the power-key or when the battery voltage
falls too low. Uncontrolled powering off happens when the battery is suddenly removed or if over-temperature
condition is detected in regulator block while in RESET mode. Then all UEME’s regulators are disabled
immediately and discrete regulators are disabled as Vbat supply disappears.
Controlled powering off
For RM-25, powering off is initiated by pressing the power key and power off sequence is activated in UEME and
SW. Basically, the power key causes UEME interrupt to UPP_WD2 and SW sets watchdog time value to zero and
as this happens, PURX is forced low and all regulators are disabled.
If the battery voltage falls below the very last SW-cutoff level, SW will power off the system by letting the UEME’s
watchdog elapse.
If thermal shutdown limit in the UEME regulator block is exceeded, the system is powered off. System reset
PURX is forced low.
Uncontrolled powering off
This happens when the battery is suddenly removed. UEME’s state machine notices battery removal after the
battery voltage has been below VCOFF- for 5 us and enters PWR_OFF mode. PURX is set low and all UEME’s
regulators are disabled.
RM-25
System module
Nokia Customer Care
9235618 (Issue 2)
Company Confidential
Page 9–9
Copyright ©2005 Nokia. All Rights Reserved.
