Quick Start Guide: LPC1768-Xplorer
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2.3 BLOCK DIAGRAM
Fig. 5
2.4 LPC1768 description
The LPC1768 is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high
level of integration and low power dissipation. The ARM Cortex-M3 is a next generation core that
offers system enhancements such as modernized debug features and a higher level of support block
integration.
LPC1768 operate at up to an 100 MHz CPU frequency. The ARM Cortex-M3 CPU incorporates a 3
stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a
third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports
speculative branches.
The peripheral complement of the LPC1768 includes up to 512 kB of flash memory, up to 64 kB of data
memory, Ethernet MAC, a USB interface that can be configured as either Host, Device, or OTG,
8 channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,
SPI interface, 3 I2C interfaces, 2-input plus 2-output IS interface, 8 channel 12-bit ADC, 10-bit DAC,
motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose
PWM, ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins.
Feature
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz.
ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD).
