Copyright © 2009 NEXCOM International Co., Ltd. All Rights Reserved.
67
NDiS 541 User Manual
Appendix C: Watchdog Timer
a
PPendix
C: W
atChdog
t
imer
WINBOND W83627UHG LPC I/O supports the Watchdog Timer functional-
ity.
1. To place the chip into the Extended Function Mode, two successive
writes of 0x87 must be applied to Extended Function Enable Registers
(EFERs, 4Eh).
2. The chip selects the Logical Device and activates the desired Logical
Devices through Extended Function Index Register (EFIR) and Extended
Function Data Register (EFDR). The EFIR is located at the same address as
the EFER, and the EFDR is located at address (EFIR+1).
First, write the Logical Device Number (i.e. 0x07) to the EFIR and then
write the number of the desired Logical Device to the EFDR. If accessing
the Chip (Global) Control Registers, this step is not required.
Secondly, write the address of the desired configuration register within
the Logical Device to the EFIR and then write (or read) the desired con-
figuration register through the EFDR (i.e. 0x08).
CR 07h. (Logical Device; Default 00h)
Bit
Read / Write
Description
7-0
R/W
Logical device number
3. The units of Watchdog Timer counter are selected at Logical Device 8,
CR[F5h], bit[3]. The time-out value is set at Logical Device 8, CR[F6h].
Writing zero disables the Watchdog Timer function. Writing any non-
zero value to this register causes the counter to load this value into the
Watchdog Timer counter and start counting down.
Logical Device 8 (WDTO#, PLED, GPIO5, 6 & GPIO Base Address)
CR F5h. (WDTO# and KBC P20 Control Mode Register; Default 00h)
Bit
Read / Write
Description
7-5
Reserved
4
R/W
1000 times faster in WDTO# count mode.
0: Disable
1: Enable
(If bit-3 is Second Mode, the count mode is
1/1000 sec.)
If bit-3 is Minute Mode, the count mode is
1/1000 min.)
3
R/W
Select WDTO# count mode.
0: Second Mode
1: Minute Mode
