NEC V850E/CA1 ATOMIC, Предварительное руководство пользователя

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Chapter 6 DMA Functions (DMA Controller)
Preliminary User’s Manual U14913EE1V0UM00
6.9 Next Address Setting Function
The DMA source address registers (DSAHn, DSALn), DMA destination address registers (DDAHn,
DDALn), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration
(n = 0 to 3).
When the terminal count is issued, these registers are automatically rewritten with the value that was
set immediately before.
Therefore, during DMA transfer, transfer is automatically started when a new DMA transfer setting is
made for these registers and the MLEn bit of the DCHCn register is set to 1 (however, the DMA transfer
end interrupt may be issued even if DMA transfer is automatically started).
Figure 6-13 shows the configuration of the buffer register.
Figure 6-13: Buffer Register Configuration
Data read
Data write
Master
register
Slave
register
Address/
count
controller
Internal bus