131
Chapter 4
Bus Control Function
Preliminary User’s Manual U15839EE1V0UM00
4.8 Wait
Function
4.8.1 Programmable wait function
(1)
Data wait control registers 0, 1 (DWC0, DWC1)
With the purpose of realizing easy interfacing with low-speed memory or with I/Os, it is possible to
insert up to 7 data wait states with respect to the starting bus cycle for each CS area.
The number of wait states can be specified by data wait control registers 0 and 1 (DWC0, DWC1)
in programming. Just after system reset, all blocks have 7 data wait states inserted.
These registers can be read/written in 16-bit units.
Cautions: 1. The internal Cache and the internal RAM area are not subject to programmable
waits and ordinarily no wait access is carried out. The internal peripheral I/O area
is also not subject to programmable wait states, with wait control performed only
by each peripheral function.
2. In the following cases, the settings of registers DWC0 and DWC1 are invalid (wait
control is performed by each memory controller).
- Page ROM on-page access
3. Write to the DWC0 and DWC1 registers after reset, and then do not change the set
values. Also, do not access an external memory area other than that for this ini-
tialization routine until initial setting of the DWC0 and DWC1 registers is finished.
However, it is possible to access external memory areas whose initialization has
been finished.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
Initial
value
DWC0
0
DW32 DW31 DW30
0
DW22 DW21 DW20
0
DW12 DW11 DW10
0
DW02 DW01 DW00 FFFFF484H 7777H
CS3
CS2
CS1
CS0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
Initial
value
DWC1
0
DW72 DW71 DW70
0
DW62 DW61 DW60
0
DW52 DW51 DW50
0
DW42 DW41 DW40 FFFFF486H 7777H
CS7
CS6
CS5
CS4
Bit Position
Bit Name
Function
14 to 12,
10 to 8,
6 to 4,
2 to 0
DWn2 to
DWn0
(n = 0 to 7)
Data Wait
Specifies the number of wait states inserted in the CSn area.
DWn2
DWn1
DWn0
Number of Wait States Inserted in CSn Space
0
0
0
No wait states inserted
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
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