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© National Instruments
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1-9
NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations
Table 1-9 lists design considerations for the schematic shown in Figure 1-3.
Table 1-9.
USB1 Host Reference Schematic Design Considerations
Consideration
Notes
USB data pair
• The USB1_DP and USB1_DN data pair is routed differentially to
the USB connector.
• On the reference carrier board, the L3 common-mode choke is not
populated, but you can populate it in your design to help with
conducted immunity or emissions.
• If you choose to populate L3, remove R79 and R82 from your
design.
• If your design does not include a common-mode choke, you can
route the USB pair directly from the USB connector to the
sbRIO-9651 SOM connector.
• U18 provides ESD protection to the USB data pair and should be
placed close to the USB connector.
USB1_CPEN
The USB1_CPEN signal must be connected to the enable of the
VBUS current limit switch (U20). This allows the sbRIO-9651 SOM
to power-cycle USB devices when the processor is reset.
USB1_VBUS
• For the USB Host port to function properly, the USB1_VBUS
signal must be connected to VBUS on the USB connector.
• This is a low-current, voltage-sense connection.
• In layout, you can treat the trace after R92 going to the sbRIO-9651
SOM connector as a data signal.
• R92 helps provide some overvoltage protection on USB1_VBUS
and should be placed close to the USB connector. NI recommends
that you use a 1 k
Ω
resistor.
• The carrier board must provide 5 V VBUS power for the USB Host
port.
• A current limit switch is required between the 5 V rail and the USB
connector.
• U20 is the current limiter.
• NI recommends that you provide 100
μ
F of capacitance on the
VBUS rail.