National Instruments PXIe-6674, Руководство пользователя

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Using Front Panel PFIs for LVDS Triggers
To allow for sending and receiving signals between system timing modules that are too fast for
single ended PFI signaling, two PFI SMA connectors can be combined to send or receive
LVDS signals.
Table 5. on page 14 shows the relation between the front panel SMA
connectors used for PFI and PFI_LVDS.
When used for trigger routing, the PFI_LVDS signals are routed to and from the FPGA. You
can independently select the output signal source for each PFI_LVDS line from one of the
following sources:
•
Another PFI<0..5>
• Another PFI pair in LVDS mode
• PXI_TRIG<0..7>
• PXI_STAR
• Global software trigger
• PFI synchronization clock
• PXIe_DSTARB
• Steady logic high or low
The PFI synchronization clock is also used for the PFI_LVDS and may be one of the following
signals:
•
Clock Generation
• PXI_CLK10
• PXIe_CLK100
• CLKIN
• Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512)
• Any of the previously listed signals divided by the second frequency divider (2
m
, up to
512).
Refer to the Choosing the Type of Routing section for more information on the synchronization
clock.
Note The PFI synchronization clock is the same for all routing operations in which
PFI<0..5> or PFI_LVDS<0..2> is defined as the output, although the divide-down
ratio for this clock (full rate, first divider, second divider) may be chosen on a per
route basis.
Using the PXI Triggers
The PXI triggers go to all the slots in the chassis. All modules receive the same PXI triggers,
so PXI trigger 0 is the same for the system timing slot as it is for Slot 3, and so on. This feature
makes the PXI triggers convenient in situations where you want, for instance, to start an
acquisition on several devices at the same time because all modules will receive the same
trigger.
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