Block Diagrams
Figure 5. FPGA Carrier Block Diagram
Synchronization
Gen3 x8 PCIe
FPGA
DRAM
Bank 1
+12 V
I/O Module Mezzanine Connector
DIO Connector
Flash
Power Supplies
+12 V, +3.3 V
PXIe Bac
kplane
Module Clocking
MGTs
Configuration, GPIO
+1.8 V
+5 V
DStarB, DStarC
PXI Triggers
PXIe_CLK100
PXI_CLK10
Reference
GPIO
Clock
MGTs
DRAM
Bank 0
PXIe-6594 Getting Started Guide
|
© National Instruments
|
11