National Instruments PCIe-6593, Руководство по началу работы

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Table 4. Available Pins on the QSFP+ Connectors (Continued)
Pin Symbol Name/Description
32 GND Ground
33 Tx3p Transmitter Non-Inverted Data Input
34 Tx3n Transmitter Inverted Data Input
35 GND Ground
36 Tx1p Transmitter Non-Inverted Data Input
37 Tx1n Transmitter Inverted Data Input
38 GND Ground
Block Diagrams
Figure 6. FPGA Carrier Block Diagram
DIO Connector
(Front Panel)
Adapter Module
Connector
+5 V
+1.8 V
+12 V
GPIO
Configuration, GPIO
MGTs
Reference Clock
Power Supplies
Flash
FPGA
Triggers
Clk 100
Gen3 x8 PCIe
+12 V, +3.3 V
+12 V
Clk 10
Module Clocking
Synchronization PLL
DRAM Bank 0
(2 GB)
DRAM Bank 1
(2 GB)
Synchronization
Connector
PCIe
Connectors
MGTs
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