Appendix B
Register-Level Programming — Interrupt Control Register 1
PCI-DIO-96/PXI-6508/PCI-6503 User Manual
B-10
ni.com
Register Description for the Interrupt Control Registers
There are two interrupt control registers on your DIO board. One of these registers has
individual enable bits for the two interrupt lines from each of the 82C55A devices. The other
register has a master interrupt enable bit and two bits for the timed interrupt circuitry. Of the
latter two bits, one bit enables counter interrupts, while the other selects counter 0 or
counter 1. This appendix lists the bit maps and signal definitions.
Interrupt Control Register 1
Address:
Base a 14 (hex)
Type:
Write-only
Word Size:
8-bit
Bit Map (PCI-DIO-96/PXI-6508):
Bit Map (PCI-6503):
Bit
Name
Description
7–2
X
Reserved on the PCI-6503.
7
DIRQ1
PPI D Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI D sends an interrupt, INTRB, to the computer. If this
bit is cleared, PPI D does not send the interrupt INTRB to
the computer, regardless of the setting of INTEN.
6
DIRQ0
PPI D Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both set,
PPI D sends an interrupt, INTRA, to the computer. If this
bit is cleared, PPI D does not send the interrupt INTRA to
the computer, regardless of the setting of INTEN.
7
6
5
4
3
2
1
0
DIRQ1
DIRQ0
CIRQ1
CIRQ0
BIRQ1
BIRQ0
AIRQ1
AIRQ0
7
6
5
4
3
2
1
0
X
X
X
X
X
X
AIRQ1
AIRQ0
